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The 63F09: a 6809-derived 8/16/32-bit CPU
The 63F09 is a custom processor, designed from scratch in VHDL by its author (running on real FPGA hardware), that extends the classic Motorola 6809 8-bit CPU into a three-level family: the base (…)
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GNU binutils
Tuesday 8 September 2026, by // Tools
A 63F09 port has been added to GNU binutils, including as (assembler), ld (linker), gdb (debugger) and a disassembler. As A09 was the first assembler for 63F09, GNU binutils were tortured until A09 and binutils produce the same binary outputs.
GNU binutils can be downloaded in section files.
To obtain a 63F09 toochain, configure script has to be run with —target=m6809.
BAC 63F81
Friday 23 August 2024, by // Peripherals
The shared bus arbiter 63F81
On a multi-core 63F09 build, all cores share a single external bus interface — one set of address, data, and control pins. 63F81.vhd instantiates one DMC_63F41 (with its own L1 cache, see the companion document) per core, and arbitrates which core’s signals actually drive that shared interface at any given moment.
One master at a time, chosen by a sticky round robin
The arbiter tracks a single integer, SIGNAL_LAST_ACTIVE_CPU — the index of the core (…)
DMC 63F41
Friday 23 August 2024, by // Peripherals
The 63F09 L1 data cache (DMC 63F41)
Each 63F09 core embeds its own private L1 data cache. It is a direct-mapped, write-through cache: every store is propagated to external memory immediately, and no dirty write-back ever happens.
A write-back policy would require flushing on every context switch and would delay writes aimed at memory-mapped peripherals — both unacceptable for this design. (…)
PTM
Monday 17 June 2024, by // Programming examples
``` ORG $FFFFFF00 LDMD #$31 LDS #$FFFE0000 LDU #$FFFDF000 * Direct mode: address is built with DS:DP:8 bits offset LDDS #$FFFE LDDP #$F0 * Configure PIA0 (PIA0(0) <= 1). * PIA0(0) is connected to PTM1.G(3) LDA #%00000000 STA <PIA0+1 LDA #%00000001 STA <PIA0 LDA #%00000100 STA (…)
Read more »SPI
Monday 17 June 2024, by // Programming examples
``` ORG $FFFFFF00 LDMD #$31 LDS #$FFFF0000 LDU #$FFFEF000 * Direct mode: address is built with DS:DP:8 bits offset LDDS #$FFFF LDDP #$00 * SPI0 * Internal registers: * SPI0+0: data register * SPI0+1: control register
* SPI0 control register * Configure divisor (1’000’000) LDA #%00000001 STA TX_EMPTY = 1 * TST Z=0 => TX_EMPTY = 1 * (…)
TWI
Friday 14 June 2024, by // Programming examples
Example ``` ORG $FFFF0000 LDMD #$31 LDS #$FFFE0000 LDU #$FFFDF000 * Direct mode: address is built with DS:DP:8 bits offset * i2c controller is at $FFFEB000-$FFFEB003 LDDS #$FFFE LDDP #$B0 * TWI0 control register LDA #%00000000 ; polling mode STA <TWI0+2 * Set TWI0 clock divisor LDD #0 STD <TWI0+4 * Set slave (…)
Read more »ROM initialization
Friday 14 June 2024, by // Tools
System on chip contains 64 Kbytes of read only memory between addresses $FFFF0000 and $FFFFFFFF. This memory is created with RAM blocks and initialized in a file created by memblcks.rpl tool.
memblcks.rpl is a program written in RPL/2 and takes a SREC file generated by A09 assembler in 32 bits mode. It splits S-records into bits arrays to create a usable 27F512.vhd file.
This tool is (…)
RAM 61F512
Friday 14 June 2024, by // Peripherals