SoC 63F09 is a FPGA (Artix7 Ultrascale+ XCAU25) that contains:

• 1 * BAC 63F81 (bus arbitration controller)
  • 1 to 8 * CPU 63F09, each CPU contains:
    • 1 * CLK 63F75 (clock generator)
    • 1 * MMU 63F29 (optional, one MMU per CPU)
    • 1 * DMC 63F41 (optional, direct mapped cache controller, write through) with 64 KB of level-1 full speed memory cache
• 1 to 8 * FPU 63F39 (optional, system can use a FPU for each CPU core or a shared one)
• 1 * DMA 63F44 controller (32 bits)
• 1 * AMC 63F42 (associative mapped cache controller, write back) with 256 KB of cache memory that acts as a level-2 cache
• 5 * PIA 63F21 (40 bits), each 63F21 is a half MC6840
• 2 * ACIA 63F50
• 2 * PTM 63F40
• 1 * SPI 63F52 (master or slave)
• 1 * TWI 63F54 (i2c master only)
• 1 * WDG 63F46 (watchdog timer)
• 1 * ROM64K 27F512 (monitor at $F:FFFF:0000 - $F:FFFF:FFFF), full speed
• 1 * RAM64K 61F512 (for monitor usage, at $F:FFFF:C000 - $F:FFFF:CFFF), full speed

SoC can be used with a companion FPGA that contains:

• 1 * 63F82 PCIe controller (Gen3, *16)
• 1 * 63F85 DDR4 controller
• 1 * 63F89 ETH (Ethernet 1000/100/10 full duplex)
• 1 * 63F88 USB 2.0
• 1 * 63F43 SATA interface
• 1 * 63F45 video adapter

CPU core runs at 140 MHz in a Artix7 Ultrascale+. CPU only uses around 48’000 LUT’s and 3’000 flip-flops, FPU 10’000 LUT’s and 4’000 flip-flops.

In an Artix7 Ultrascale+ XCAU25, SoC runs with shared FPU, two CPU with DMC and MMU (64 indirections, 4 rings), BAC, DMA, AMC ans slow peripherals.