PTM

Monday 17 June 2024, by 63F09 // Programming examples

    ORG     $FFFFFF00
    LDMD    #$31
    LDS     #$FFFE0000
    LDU     #$FFFDF000
* Direct mode: address is built with DS:DP:8 bits offset
    LDDS    #$FFFE
    LDDP    #$F0
    *   Configure PIA0 (PIA0(0) <= 1).
    * PIA0(0) is connected to PTM1.G(3)
    LDA     #%00000000
    STA     <PIA0+1
    LDA     #%00000001
    STA     <PIA0
    LDA     #%00000100
    STA     <PIA0+1
    LDA     #%00000001
    STA     <PIA0
* 1 : source (0 : external)
* 2 : mode (0 : 16 bits)
* 6 : interrupt enabled
* Write to CR2
    LDDP    #$D0
    LDA     #%00000001
    STA     <PTM1+1
* Write to CR1 (CR2(0) = 1)
    LDA     #%00000000
    STA     <PTM1
* Write to CR2
    LDA     #%00000000
    STA     <PTM1+1
* Write to CR3 (CR2(0) = 0)
    LDA     #%11111010
    STA     <PTM1
* Write to LATCH3
    LDD     #$0020
    STD     <PTM1+6
* PTM1.3 : Timer interval mode
* Now, try to start timer
    BSR     EDGE
    BSR     EDGE
    STA     <PIA0
* Now, try to restart timer
    LDB     #10
L1:
    DECB
    BNE L1
    LDDP    #$F0
    LDA     #%00000000
    STA     <PIA0

LOOP:
    BRA     LOOP

* Abort simulation
    FCB     $CF

EDGE:
    LDDP    #$F0
    LDA     #%00000000
    STA     <PIA0
    LDA     #%00000001
    STA     <PIA0
    RTS

    ORG     $FFFFFF80
    PSHS    D,W,DP
    LDDP    #$D0
    * Read status register
    LDB     <PTM0+1
    * Read timers
    LDW     <PTM0+2
    LDW     <PTM0+4
    PULS    D,W,DP
    RTI

    ORG     $FFFFFFA0
    PSHS    D,W,DP
    LDDP    #$D0
    * Read status register
    LDB     <PTM1+1
    * Read timers
    LDW     <PTM1+6
    PULS    D,W,DP
    RTI

TWI0    EQU $FFFEB000
    
SPI0    EQU $FFFEC000
    
PTM0    EQU $FFFED000
PTM1    EQU $FFFED008
    
ACIA0   EQU $FFFEE000
ACIA1   EQU $FFFEE004
    
PIA0    EQU $FFFEF000
PIA1    EQU $FFFEF002
PIA2    EQU $FFFEF004
PIA3    EQU $FFFEF006
PIA4    EQU $FFFEF008


    * PTM1 interrupt
    ORG     $FFFFFFE8
    FDB     $FFA0

    * PTM0 interrupt
    ORG     $FFFFFFEA
    FDB     $FF80

    ORG     $FFFFFFF0
    FDB     $0000
    FDB     $0000
    FDB     $0000
    FDB     $0000
    FDB     $0000
    FDB     $0000
    FDB     $0000
    FDB     $FF00

    END