Peripherals
Latest update : 23 August 2024.
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BAC 63F81
Friday 23 August 2024, by // Peripherals
The shared bus arbiter 63F81
On a multi-core 63F09 build, all cores share a single external bus interface — one set of address, data, and control pins. 63F81.vhd instantiates one DMC_63F41 (with its own L1 cache, see the companion document) per core, and arbitrates which core’s signals actually drive that shared interface at any given moment.
One master at a time, chosen by a sticky round robin
The arbiter tracks a single integer, SIGNAL_LAST_ACTIVE_CPU — the index of the core (…)
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DMC 63F41
Friday 23 August 2024, by // Peripherals
The 63F09 L1 data cache (DMC 63F41)
Each 63F09 core embeds its own private L1 data cache. It is a direct-mapped, write-through cache: every store is propagated to external memory immediately, and no dirty write-back ever happens.
A write-back policy would require flushing on every context switch and would delay writes aimed at memory-mapped peripherals — both unacceptable for this design. Write-through sidesteps both problems at the cost of writing external memory on every store, hit or (…)
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RAM 61F512
Friday 14 June 2024, by // Peripherals
ROM 27F512
Friday 14 June 2024, by // Peripherals
System on chip contains a 64 Kbytes ROM between $FFFF0000 and $FFFFFFFF. Memory is created with RAM blocks in a read only configuration.
This ROM is hardcoded and initialized with memblcks.rpl.
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MMU 63F29
Friday 14 June 2024, by // Peripherals
* Adresse du vecteur RESET ORG $FFFF0010
LDMD #$31
* Ring 0 : on mappe la page des vecteurs d’interruption, MMU inactive LDQ #$FFFFFF00 ; adresse logique que l’on doit atteindre. ; seuls les bits 31 à 12 sont pertinents, soit ; $FFFF:F000. STQ >TAG_STAGING
LDQ #$09FFFFFF ; adresse physique de la page. ; $09 : read, always mapped (…)
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SPI 63F52
Friday 14 June 2024, by // Peripherals
This controller acts as master or slave SPI device. External signals MISO MOSI SCLK CS (16 bits)
In slave mode, CS(0) is mandatory SS_n signal. In master mode, CS is used to address slaves’s chip select lines. This controller can directly drive 16 SPI slaves or more slave with an additional address decoder. Internal registers Registers Address Access 7 6 5 4 3 2 1 0 base + 0 when CC(0) = 0 read RX register write TX register base + 0 when CC(0) = 1 (…)
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TWI (i2c) 63F54
Friday 14 June 2024, by // Peripherals
Internal registers Registers Address Access 7 6 5 4 3 2 1 0 base + 0 read RX register write TX register base + 1 read Current start register (cleared when transaction begins) write Start register DC [1] DC DC soft reset stop after slave’s ack master ack read/not write start request base + 2 read/write Control register RX data ready TX empty RX IRQ enabled TX IRQ enabled ACK received ACK error busy 10 bits address base + 3 read Status register READY (…) Read more »
PTM 63F40
Friday 14 June 2024, by // Peripherals
This programmable timer has been designed to be compatible with regular MC6840.
The programmable timer (PTM 63F40)
PTM_63F40 is modelled on the classic 6840 PTM: three independent timer/counter channels, each with its own control register, 16-bit latch, gate input, clock input, and output pin.
Three identical channels
Each channel keeps a 19-bit down-counter (a 16-bit value plus a 3-bit prescale-by-8 tail), reloaded from its own 16-bit latch register whenever it reaches zero, on (…)
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PIA 63F21
Friday 14 June 2024, by // Peripherals
This component runs as a regular MC6821. Please note that 63F21 only contains half MC6821.
The parallel interface (PIA 63F21)
PIA_63F21 is a peripheral interface adapter modelled on the classic 6821 PIA — but, as the source itself warns, only half of one: a single 8-bit bidirectional port with its two handshake lines (C1, C2), not the real chip’s two independent ports.
One port, direction set per bit
PORT_D is a genuine bidirectional bus, built from one IOBUF primitive per bit, each (…)
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ACIA 63F50
Friday 14 June 2024, by // Peripherals
This asynchronous serial interface has been designed to be compatible with regular MC6850.
The serial interface (ACIA 63F50)
ACIA_63F50 is a UART modelled on the classic 6850 ACIA, drawing on two well-known open designs (a miniUART and John Kent’s own 6850 implementation) as a starting point. It exposes the same two-register, software-visible model as the original chip, with one deliberate departure from it.
Status and control (address + 0)
Reading this address returns the status (…)
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