The 63F09 is a custom processor, designed from scratch in VHDL by its author (running on real FPGA hardware), that extends the classic Motorola 6809 8-bit CPU into a three-level family: the base 6809 instruction set, a superset compatible with the Hitachi HD6309 (“6309 native mode”), and the 63F09 itself, which adds a 32-bit addressing/register mode and an optional hardware floating-point unit (63F09HF). Unlike the original 6809, which was strictly an 8/16-bit microcontroller-class chip, the 63F09 in its 32-bit mode addresses up to 64 GB of memory — the design target is a real, general-purpose CPU, not a microcontroller.

Register file

The 63F09 keeps the 6809’s original registers (PC, S, U, X, Y, DP, CC, A, B) and layers new ones on top as each mode is unlocked:

– E, F, V become available from 6309-native mode onward;
– DS, a second direct-page selector, is 63F09-only;
– composite pseudo-registers combine the raw ones: D = A:B (always available), W = E:F (6309+), Q = D:W (6309+, always 32 bits — available in both 16-bit and 32-bit CPU modes, unlike X/Y/U/S/V which only widen to 32 bits in 63F09 32-bit mode), and O = Q:V, a 64-bit “octo” register available in 63F09 32-bit mode only.

A notable ABI property: on this port’s calling convention, every general-purpose register is caller-saved. There is no callee-saved register set to spill in a prologue, which simplifies function entry/exit code generation considerably.

Direct-page addressing

Like the original 6809, the 63F09 keeps a fast “direct page” addressing mode selected by the DP register (and, in 32-bit mode, an additional DS register selecting a 16 MB window). A GCC backend pass on this port automatically detects small static/global variables accessed repeatedly inside a loop, forces them into a 256-byte-aligned page, and rewrites in-loop accesses to use this one-byte-shorter, faster addressing form — entirely automatically, with no source-level annotation required.

Hardware floating point

The optional 63F09HF variant adds a real hardware FPU: a 16-deep stack of FP0-FP15 registers (single and double precision), fused multiply-add, square root, and the usual arithmetic/comparison/conversion set. Comparisons report their result through the CPU’s own condition-code register rather than the FP stack, which turned out to be exactly the contract GCC’s stack-register allocator (originally written for the x87) expects.

Toolchain and software support

The 63F09 is backed by a genuinely working, from-scratch GNU toolchain port: binutils (assembler, linker, disassembler), GDB, and a GCC backend supporting C and Fortran, all built up and verified against real compiled and linked output rather than assumed correct. A newlib C library port covers four distinct hosting environments — bare metal, two vintage 6809 operating systems (FLEX9 and UniFLEX), and a simulated development SoC with a real UART console — selected at link time via dedicated crt0 startup files and linker emulations.

Advantages

– A simple, well-understood 8-bit instruction set as its foundation, extended rather than replaced — 6809 and 6309 object code and assembly-level habits remain directly relevant.
– Genuine 32-bit addressing and a real hardware FPU bolted onto that familiar base, without abandoning its register model or addressing-mode philosophy.
– Automatic direct-page optimization gives small, loop-hot data a real, compiler-managed speed win with zero source changes.
– An entirely caller-saved register convention keeps function prologues/epilogues trivially cheap.
– A complete, real GCC/binutils/newlib toolchain exists today: C and Fortran programs can actually be compiled, assembled, linked, and (statically) inspected, not just theorized about.
– Being an open, from-scratch VHDL design that runs on FPGA, the whole system — CPU, ISA, and toolchain — is fully inspectable and modifiable, which has made it practical to find and fix real bugs by cross-checking compiler output against the hardware description directly.

Limitations and open issues

– Some hardware-backed arithmetic (64x64 multiply, 8x8 multiply) is not yet exposed as GCC instruction patterns, so the compiler still emits slower software fallbacks for cases the CPU could handle directly.
– libgfortran, GCC’s Fortran runtime, is too large to fit in the 64 KB address space of the 16-bit submodes once anything beyond trivial I/O is linked in — full-featured Fortran I/O is presently a 32-bit-mode-only proposition.

In short

The 63F09 is best understood as “what if the 6809 had kept growing” rather than a clean-sheet modern design: it trades the novelty of a from-scratch ISA for the comfort of a genuinely simple, fully understood 8-bit ancestor, extended just enough — 32-bit addressing, a real FPU, automatic direct-page optimization — to make real systems.