CPU 63F09
Latest update : 23 September.
The 63F09 processor is written entirely in VHDL-2008. It can be synthesised in an FPGA from the Artix7 family (AMD), and reaches a frequency of 600 MHz (25 * 24 MHz), knowing that most instructions are executed in fewer clock cycles than on a real HD6309.
The address bus is 32 bits wide, data bus only 8 bits wide and this processor has twenty-seven interrupt request lines: NMI, FIRQ, IRQ and twenty-four EIRQ (extended IRQ) which are active on edge or level.
The processor always starts up in 6809 mode (16 bits). Before loading the S pointer for the first time, you can switch its operation to mode 6309 or 63F09 with or without FPU.
The floating-point unit consists of a stack of sixteen 64 bits registers capable of processing single-precision and double-precision floats (addition, multiplication, substractions, divisions, square roots, comparisons, multiplications with accumulations).
In 63F09 mode, the arithmetic logic unit has 8-, 16- and 32-bits signed and unsigned hardwired multiplications. Similarly, it has 16-, 32- and 64-bits signed and unsigned hardwired divisions.
Latest articles
The 63F09: a 6809-derived 8/16/32-bit CPU
Wednesday 23 September 2026, by // CPU 63F09
The 63F09 is a custom processor, designed from scratch in VHDL by its author (running on real FPGA hardware), that extends the classic Motorola 6809 8-bit CPU into a three-level family: the base 6809 instruction set, a superset compatible with the Hitachi HD6309 (“6309 native mode”), and the 63F09 itself, which adds a 32-bit addressing/register mode and an optional hardware floating-point unit (63F09HF). Unlike the original 6809, which was strictly an 8/16-bit microcontroller-class chip, the (…) Read more »
Opcodes
Tuesday 28 May 2024, by // CPU 63F09
Warning: in 63F09 mode (32 bits), there is no 0 or Z (zero) register. Nevertheless, in 6309 mode (16 bits), Z is usable with EXG and TFR opcodes.
In 63F09 mode, EXG and TFR operands are modified to exchange or transfer new Q and DS registers.
The following table lists the processor instructions and cycle counts for the MC6809, HD6309, and 63F09. Base page ($00)
Opcodes $00-$0F MnemonicBytesOpcodeAddressing modeMC6809HD630963F09 16-bit63F09 32-bit NEG 2 $00 Direct 6 5 5
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Internal registers
Tuesday 28 May 2024, by // CPU 63F09
MD register is always accessible as it changes the processor’s operating mode. Due to internal data path, 0 or Z (zero) register is available for transfer and exchange instructions. 6809 mode Registers 8 bits 8 bits A B Virtual D (16 bits) Z DP CC MD 16 bits X Y U S PC
MD bits MD DZ IL FPU 32 IS ED FM EM EM: 0: 6809 mode 1: 6309 mode FM: 0: FIRQ and EIRQ’s treated as fast interrupt requests 1: FIRQ and EIRQ’s treated as interrupt request ED: 0: EIRQ (…)
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FPU
Tuesday 28 May 2024, by // CPU 63F09
The floating-point unit 63F39
The 63F09’s FPU is split cleanly in two: a 16-level register stack hosted in the CPU core itself, and a separate, stateless execution engine (referred to as 63F39) that the core drives through a small request/response interface. The core owns all FPU state; the engine only computes.
A 16-level, RPN-style operand stack, not a flat register file
REG_FP is sixteen 64-bit registers, REG_FP(0) to REG_FP(15) — but software addresses them as stack levels, not (…)
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A 8/64 bits CPU
Tuesday 28 May 2024, by // CPU 63F09
63F09 is a modern CPU full compatible with old MC6809. It presents only one difference with HD6309, it don’t have a 0 register.
If the first instruction after reset is LDMD, CPU can enter in 6309 mode (16 bits) or 63F09 mode (32 bits) with or without FPU.
In 63F09 mode, there are a lot of new instructions. For example: hardwired multiplications and division (until 64 bits); 32 and 64 bits arithmetic; FPU that handle simple and double precision floats; 32 bits addresses (36 bits with (…)
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