ORG     $FFFFFF00
    LDMD    #$31
    LDS     #$FFFF0000
    LDU     #$FFFEF000
* Direct mode: address is built with DS:DP:8 bits offset
    LDDS    #$FFFF
    LDDP    #$00
* SPI0
* Internal registers:
* SPI0+0: data register
* SPI0+1: control register

* SPI0 control register
* Configure divisor (1'000'000)
    LDA     #%00000001
    STA     <SPI0+1
    LDD     #5
    STD     <SPI0
    LDA     #%00000001
    STA     <SPI0+1
    LDW     <SPI0
* Configure SPI0
    LDA     #%00100000
    STA     <SPI0+1
* Send data
    JSR     WAIT
    LDA     #$AA
    STA     <SPI0
    JSR     WAIT
    LDA     #$A5
    STA     <SPI0
    JSR     WAIT2

* Abort simulation
    FCB     $CF

WAIT:
    LDB     <SPI0+1
    ANDB    #$40
    TSTB
* loop while SPI0_CC(TX_EMPTY) = 0
* SPI0_CC and #$40 = #$40 => TX_EMPTY = 1
* TST Z=0 => TX_EMPTY = 1
* TST Z=1 => TX_EMPTY = 0
    BEQ     WAIT
    RTS

WAIT2:
    LDW     #500
BOUCLE:
    DECW
    BNE     BOUCLE
    RTS

    * IRQ SPI0
    ORG     $FFFFFF80
    * Read SPI RX register to release interrupt request
    PSHU    B
    LDB     <SPI0
    PULU    B
    RTI

TWI0    EQU $FFFEB000
    
SPI0    EQU $FFFEC000
    
PTM0    EQU $FFFED000
PTM1    EQU $FFFED008
    
ACIA0   EQU $FFFEE000
ACIA1   EQU $FFFEE004
    
PIA0    EQU $FFFEF000
PIA1    EQU $FFFEF002
PIA2    EQU $FFFEF004
PIA3    EQU $FFFEF006
PIA4    EQU $FFFEF008
    
    * TWI0 interrupt
    ORG     $FFFFFFDA
    FDB     $FF80
    
    ORG     $FFFFFFF0
    FDB     $0000 
    FDB     $0000
    FDB     $0000
    FDB     $0000
    FDB     $0000
    FDB     $0000
    FDB     $0000
    FDB     $0000
    
    END