SoC 63F09 is a FPGA (Artix7 XC7A100) that contains:

• 1 * BAC 63F81 (bus arbitration controller)
  • 1 to 8 * CPU 63F09, each CPU contains:
    • 1 * MMU 63F29
    • 1 * FPU 63F39 (optional, system can use a shared FPU)
    • 1 * DMC 63F41 (direct mapped cache controller, write through) with 64 KB of level-1 full speed memory cache
• 1 * FPU 63F39 (optional, system can use a FPU for each CPU core)
• 1 * DMA 63F44 controller (32 bits)
• 1 * hyperram controller
• 1 * PCIe controller
• 1 * AMC 63F42 (associative mapped cache controller, write back) with 256 KB of cache memory that acts as a level-2 cache
• 5 * PIA 63F21 (40 bits), each 63F21 is a half MC6840
• 2 * ACIA 63F50
• 2 * PTM 63F40
• 1 * SPI 63F52 (master or slave)
• 1 * TWI 63F54 (i2c master only)
• 1 * ETH (Ethernet 1000/100/10 full duplex)
• 1 * USB 1.1
• 1 * PS/2 adapter
• 1 * SATA interface
• 64 KB of full speed PROM ($F FFFF 0000 - $F FFFF FFFF);

RAM is not included in SoC.