TWI (i2c) 63F54
Friday 14 June 2024, by 63F09 //
Peripherals
Internal registers
Registers
| Address | Access | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|
| base + 0 |
read |
RX register |
| write |
TX register |
| base + 1 |
read |
Current start register (cleared when transaction begins) |
| write |
Start register |
| DC [1] |
DC |
DC |
soft reset |
stop after slave’s ack |
master ack |
read/not write |
start request |
| base + 2 |
read/write |
Control register |
| RX data ready |
TX empty |
RX IRQ enabled |
TX IRQ enabled |
ACK received |
ACK error |
busy |
10 bits address |
| base + 3 |
read |
Status register |
| READY (00000001) |
| READY (00000001) |
| START (00000010) |
| STOP (00000011) |
| READ (00000100) |
| WRITE (00000101) |
| MASTER ACK (00001000) |
| NO MASTER ACK (00001001) |
| SLAVE ACK after address (00010000) |
| SLAVE ACK after data (00010001) |
| ERROR (10000000) |
| base + 3 |
write |
DC |
DC |
DC |
DC |
DC |
DC |
DC |
DC |
| base + 4 |
read/write |
Clock divisor (MSB) |
| base + 5 |
read/write |
Clock divisor (LSB) |
| base + 6 |
read/write |
Slave address (MSB) |
| base + 7 |
read/write |
Slave address (LSB) |