SPI 63F52

Friday 14 June 2024, by 63F09 // Peripherals

This controller acts as master or slave SPI device.

External signals

  • MISO
  • MOSI
  • SCLK
  • CS (16 bits)

In slave mode, CS(0) is mandatory SS_n signal. In master mode, CS is used to address slaves’s chip select lines. This controller can directly drive 16 SPI slaves or more slave with an additional address decoder.

Internal registers

Registers
Address Access 7 6 5 4 3 2 1 0
base + 0 when CC(0) = 0 read RX register
write TX register
base + 0 when CC(0) = 1 read/write Clock divisor (MSB)
base + 1 read/write Control register
BUSY_n/RX data ready TX empty RX IRQ enabled TX IRQ enabled CPOL CPHA Slave SPI Clock divisor access
base + 1 when CC(0) = 1 read/write Clock divisor (LSB)
base + 2 when CC(0) = 0 read/write Chip select register (MSB)
base + 3 when CC(0) = 0 read/write Chip select register (LSB)

Notes

Please note that CS(0) is only used to read or write clock divisor register. This bit returns to 0 after first access to clock register (LSB). Chip select register cannot be selected when CS(0) = 1 (write operation is ignored and read operation always returns $00).