This programmable timer has been designed to be compatible with regular MC6840.

The programmable timer (PTM 63F40)

PTM_63F40 is modelled on the classic 6840 PTM: three independent timer/counter channels, each with its own control register, 16-bit
latch, gate input, clock input, and output pin.

Three identical channels

Each channel keeps a 19-bit down-counter (a 16-bit value plus a 3-bit prescale-by-8 tail), reloaded from its own 16-bit latch register whenever it reaches zero, on reset, or when told to restart. Three things gate whether — and how — a channel actually counts:

• Clock source (control bit 1) — either the channel’s own external pin C_n, or the shared SYSCLK.
• Gate (G_n) — held low, or a fresh negative edge on it, is what lets the counter run at all; the comment in the source is explicit: “Counter is enabled by an absence of a timer reset condition and a logic zero at the gate input.”
• Mode (control bits 5-3) — continuous: the counter free-runs, auto-reloading and toggling the channel’s output (O) and its interrupt flag every time it reaches zero, restarted by a gate edge, a fresh write to the latch, or reset. Single-shot: a small internal state machine (STAGE) produces exactly one active-high pulse on O, timed by the counter, then returns to idle until the next gate
  edge or latch write starts it again.

Channel 3 has one extra option of its own: control bit 0 lets it decrement by the full 19-bit granularity (one step of the prescaler at a time) instead of the usual 8 — the mechanism a chained configuration would use to build slower rates out of channel 3’s own countdown for the other channels.

Register map

Three address bits select, on read, the shared status register or one of the three channels’ current 16-bit counter value (high or low byte); writes target the corresponding control register or latch register instead. Reading the status register also latches which of the three channels are pending, for whatever software wants to do with that snapshot (PENDING_IRQ).

Interrupt aggregation

Each channel has its own interrupt-enable bit (control register bit 6) and its own pending flag; the global status register bit 7 is simply the OR of the three (flag and its own enable), and IRQ_n follows that bit directly once reset is released. As with the other peripherals on this bus, MRDY is tied to '1' — the PTM never inserts a wait state.