This asynchronous serial interface has been designed to be compatible with regular MC6850.

The serial interface (ACIA 63F50)

ACIA_63F50 is a UART modelled on the classic 6850 ACIA, drawing on two well-known open designs (a miniUART and John Kent’s own 6850 implementation) as a starting point. It exposes the same two-register, software-visible model as the original chip, with one deliberate departure from it.

Status and control (address + 0)

Reading this address returns the status register — interrupt request, receive parity/overrun/framing errors, CTS level, DCD level, transmit-buffer-empty, and receive-data-ready, one bit each. Writing it sets the control register instead: an RX-interrupt enable bit, two bits selecting the TX behaviour (interrupt on/off, RTS asserted or cleared, or a forced break condition), three bits picking the word format (7 or 8 data bits, 1 or 2 stop bits, odd, even or no parity — eight combinations, matching the original chip’s own encoding), and two bits for the baud-rate divider (÷1, ÷16, ÷64, or a software reset of the whole peripheral).

Data (address + 1)

A read returns the last received character and clears receive-data-ready; a write queues a character for transmission and clears transmit-buffer-empty until it has gone out.

Where this design departs from a real 6850: no external serial clock pins

A genuine 6850 takes its transmit and receive bit clocks from external pins. This implementation does not — the source carries an explicit warning that serial clocks are generated internally from SYSCLK and are not available on the serial bus. In its place, address + 2 and address + 3 expose a programmable divisor that derives the actual baud clock from SYSCLK on-chip. Software configures a baud rate by programming this divisor together with the ÷1/÷16/÷64 control bits, rather than by wiring an external baud-rate generator to the chip.

RS232 handshake

Beyond RxD/TxD themselves, the peripheral drives RTS_n from the control register’s own TX-control bits, and reads CTS_n/DCD_n back into the status register — the same modem-control handshake the original 6850 offers, just without a way to drive its own bit-rate off the bus. As with the other peripherals on this bus, MRDY is tied to '1': the ACIA never inserts a wait state of its own on the CPU side, independently of how fast the actual serial line runs.