MD register is always accessible as it changes the processor’s operating mode. Due to internal data path, 0 or Z (zero) register is available for transfer and exchange instructions.

6809 mode

MD bits

• EM:
  • 0: 6809 mode
  • 1: 6309 mode
• FM:
  • 0: FIRQ treated as fast interrupt request
  • 1: FIRQ treated as interrupt request
• ED:
  • 0: EIRQ [1] active on level
  • 1: EIRQ active on edge
• IS :
  • 0: interrupt requests are not disabled after an interrupt routine is called.
  • 1: interrupt requests are disabled after an interrupt routine is called until S stack pointer is loaded with a new value. Used to change CPU context with MMU.
• 32 : ignored if EM is set to 0.
  • 0 : 6309 mode (16 bits)
  • 1 : 63F09 mode (32 bits)
• FPU : ignored if EM is set to 0.
  • 0 : no FPU
  • 1 : IEEE FPU
• IL : output flag, illegal instruction
• DZ : output flag, division by zero

6309 mode

Note that 63F09 in full 63F09 mode does not contain 0 or Z (zero) register.

63F09 mode with FPU

Please note that MD register is in 63F09 mode a 32 bits register. Eight LSB bits act as 6309 standard MD register. Other bits are used as EIRQ masks.

FPUCC
FPUCC contains three bits for rounding mode and five bits for status. It cannot be direcly addressed.

• RND2, RND1, RND0 are set by SETRNE, SETRTZ, SETRDN, SETRUP, SETRMM or SETDYN instruction.
• other bits are used as flags set by FPU:
  • NV : invalid result
  • DZ : division by zero
  • OF : overflow
  • UF : underflow
  • NX : inexact

These flags can be tested by (L)BNV, (L)BDZ, (L)BOV, (L)BUN and (L)BIX instructions. Two other branch instructions (L)BFT and (L)BFF are used to test boolean result of FPU operation (for example FCMPS).