63F09

BAC 63F81

63F09 — 2024-08-23T17:22:19Z

- Peripherals

DMC 63F41

63F09 — 2024-08-23T17:22:01Z

DMC 63F41 is a level-1 direct mapped cache controller. It is not configurable.

Characteristics:

full speed;
direct mapped;
write through;
64 KB of synchronous RAM;
usable in SMP configuration as it contains a cache invalidation subsystem.

PTM

63F09 — 2024-06-17T08:32:47Z

``` ORG $FFFFFF00 LDMD #$31 LDS #$FFFE0000 LDU #$FFFDF000 * Direct mode: address is built with DS:DP:8 bits offset LDDS #$FFFE LDDP #$F0 * Configure PIA0 (PIA0(0) <= 1). * PIA0(0) is connected to PTM1.G(3) LDA #%00000000 STA <PIA0+1 LDA #%00000001 STA <PIA0 LDA #%00000100 STA <PIA0+1 LDA #%00000001 STA <PIA0 * 1 : source (0 : external) * 2 : mode (0 : 16 bits) (…)

- Programming examples

SPI

63F09 — 2024-06-17T08:27:32Z

``` ORG $FFFFFF00 LDMD #$31 LDS #$FFFF0000 LDU #$FFFEF000 * Direct mode: address is built with DS:DP:8 bits offset LDDS #$FFFF LDDP #$00 * SPI0 * Internal registers: * SPI0+0: data register * SPI0+1: control register
* SPI0 control register * Configure divisor (1'000'000) LDA #%00000001 STA TX_EMPTY = 1 * TST Z=0 => TX_EMPTY = 1 * TST Z=1 => TX_EMPTY = 0 BEQ WAIT RTS
WAIT2: LDW #500 BOUCLE: DECW BNE (…)

- Programming examples

TWI

63F09 — 2024-06-14T06:40:13Z

i2c transaction with an 24C02 EEPROM (single and burst)

Example

 ORG $FFFF0000 LDMD #$31 LDS #$FFFE0000 LDU #$FFFDF000 * Direct mode: address is built with DS:DP:8 bits offset * i2c controller is at $FFFEB000-$FFFEB003 LDDS #$FFFE LDDP #$B0 * TWI0 control register LDA #%00000000 ; polling mode STA



ROM initialization
63F09 — 2024-06-14T06:38:34Z
System on chip contains 64 Kbytes of read only memory between addresses $FFFF0000 and $FFFFFFFF. This memory is created with RAM blocks and initialized in a file created by memblcks.rpl tool.
memblcks.rpl is a program written in RPL/2 and takes a SREC file generated by A09 assembler in 32 bits mode. It splits S-records into bits arrays to create a usable 27F512.vhd file.
This tool is downloadable from ftp site.
hilbert:[~/vhdl/63F09asmb/tests] > ./memblcks.rpl -A \"i2c.s09\" +++RPL/2 (R) version 4.1.36 (Jeudi 08/02/2024, 17:52:53 CET) +++Copyright (C) 1989 à 2023, 2024 BERTRAND Joël S315FFFF0000113D3110CEFFFE0000CEFFFDF00010C800 S315FFFF0010FFFE10C6B086009702CC0000DD04CC00C1 S315FFFF002050DD068620970086019701170000008C9A S315FFFF0030864E970086099701C603170000008B8639 S315FFFF004010970086019701C611170000007C863FB7 S315FFFF0050970086019701C605170000006D86249756 S315FFFF00600086099701C603170000005E86109700FA S315FFFF007086019701C6058D5286079701C6088D4AE9 S315FFFF008010860200105A26FC11D60086209702869C S315FFFF0090039701C6098D3386209700860197018D49 S315FFFF00A02286039701C6038D218611970086019746 S315FFFF00B0018D1086039701C6038D0FCF96028440ED S315FFFF00C027FA399602840827FA39960310378926C5 S309FFFF00D0F90F0039E7 S309FFFFFF001196003B17 S307FFFFFFD8FF0024 S315FFFFFFF000000000000000000000000000000000FD S9030000FC hilbert:[~/vhdl/63F09asmb/tests] > 


RAM 61F512
63F09 — 2024-06-14T06:37:13Z
-
Peripherals


ROM 27F512
63F09 — 2024-06-14T06:36:44Z
System on chip contains a 64 Kbytes ROM between $FFFF0000 and $FFFFFFFF. Memory is created with RAM blocks in a read only configuration.
This ROM is hardcoded and initialized with memblcks.rpl.


MMU 63F29
63F09 — 2024-06-14T06:35:58Z
-
Peripherals


SPI 63F52
63F09 — 2024-06-14T06:35:26Z
This controller acts as master or slave SPI device.
 External signals 
 MISO
 MOSI
 SCLK
 CS (16 bits)
In slave mode, CS(0) is mandatory SS_n signal. In master mode, CS is used to address slaves's chip select lines. This controller can directly drive 16 SPI slaves or more slave with an additional address decoder.
 Internal registers 

Registers
 Address  Access  7  6  5  4  3  2  1  0 


base + 0 when CC(0) = 0
read
RX register

write
TX register

base + 0 when CC(0) = 1
read/write
Clock divisor (MSB)

base + 1
read/write
Control register

BUSY_n/RX data ready
TX empty
RX IRQ enabled
TX IRQ enabled
CPOL
CPHA
Slave SPI
Clock divisor access

base + 1 when CC(0) = 1
read/write
Clock divisor (LSB)

base + 2 when CC(0) = 0
read/write
Chip select register (MSB)

base + 3 when CC(0) = 0
read/write
Chip select register (LSB)

 Notes 
Please note that CS(0) is only used to read or write clock divisor register. This bit returns to 0 after first access to clock register (LSB). Chip select register cannot be selected when CS(0) = 1 (write operation is ignored and read operation always returns $00).

Address	Access	7	6	5	4	3	2	1	0
base + 0 when CC(0) = 0	read	RX register
base + 0 when CC(0) = 0	write	TX register
base + 0 when CC(0) = 1	read/write	Clock divisor (MSB)
base + 1	read/write	Control register
base + 1	read/write	BUSY_n/RX data ready	TX empty	RX IRQ enabled	TX IRQ enabled	CPOL	CPHA	Slave SPI	Clock divisor access
base + 1 when CC(0) = 1	read/write	Clock divisor (LSB)
base + 2 when CC(0) = 0	read/write	Chip select register (MSB)
base + 3 when CC(0) = 0	read/write	Chip select register (LSB)