https://63F09.systella.fr/ en SPIP - www.spip.net https://63f09.systella.fr/local/cache-vignettes/L110xH56/kl_motorola_mc6809-0d844.jpg?1716898660 https://63F09.systella.fr/ 56 110 https://63f09.systella.fr/soc-63f09/programming-examples/article/ptm https://63f09.systella.fr/soc-63f09/programming-examples/article/ptm 2024-06-17T08:32:47Z text/html en 63F09 <p>``` <span class="caps">ORG</span> $<span class="caps">FFFFFF00</span> <span class="caps">LDMD</span> #$31 <span class="caps">LDS</span> #$<span class="caps">FFFE0000</span> <span class="caps">LDU</span> #$<span class="caps">FFFDF000</span> * Direct mode: address is built with <span class="caps">DS</span>:<span class="caps">DP</span>:8 bits offset <span class="caps">LDDS</span> #$<span class="caps">FFFE</span> <span class="caps">LDDP</span> #$F0 * Configure <span class="caps">PIA0</span> (<span class="caps">PIA0</span>(0) <= 1). * <span class="caps">PIA0</span>(0) is connected to <span class="caps">PTM1</span>.G(3) <span class="caps">LDA</span> #%00000000 <span class="caps">STA</span> <<span class="caps">PIA0</span>+1 <span class="caps">LDA</span> #%00000001 <span class="caps">STA</span> <<span class="caps">PIA0</span> <span class="caps">LDA</span> #%00000100 <span class="caps">STA</span> <<span class="caps">PIA0</span>+1 <span class="caps">LDA</span> #%00000001 <span class="caps">STA</span> <<span class="caps">PIA0</span> * 1 : source (0 : external) * 2 : mode (0 : 16 bits) (…)</p> - <a href="https://63f09.systella.fr/soc-63f09/programming-examples/" rel="directory">Programming examples</a> <div class='rss_texte'><div class="precode"><pre class='spip_code spip_code_block' dir='ltr' style='text-align:left;'><code> ORG $FFFFFF00 LDMD #$31 LDS #$FFFE0000 LDU #$FFFDF000 * Direct mode: address is built with DS:DP:8 bits offset LDDS #$FFFE LDDP #$F0 * Configure PIA0 (PIA0(0) <= 1). * PIA0(0) is connected to PTM1.G(3) LDA #%00000000 STA <PIA0+1 LDA #%00000001 STA <PIA0 LDA #%00000100 STA <PIA0+1 LDA #%00000001 STA <PIA0 * 1 : source (0 : external) * 2 : mode (0 : 16 bits) * 6 : interrupt enabled * Write to CR2 LDDP #$D0 LDA #%00000001 STA <PTM1+1 * Write to CR1 (CR2(0) = 1) LDA #%00000000 STA <PTM1 * Write to CR2 LDA #%00000000 STA <PTM1+1 * Write to CR3 (CR2(0) = 0) LDA #%11111010 STA <PTM1 * Write to LATCH3 LDD #$0020 STD <PTM1+6 * PTM1.3 : Timer interval mode * Now, try to start timer BSR EDGE BSR EDGE STA <PIA0 * Now, try to restart timer LDB #10 L1: DECB BNE L1 LDDP #$F0 LDA #%00000000 STA <PIA0 LOOP: BRA LOOP * Abort simulation FCB $CF EDGE: LDDP #$F0 LDA #%00000000 STA <PIA0 LDA #%00000001 STA <PIA0 RTS ORG $FFFFFF80 PSHS D,W,DP LDDP #$D0 * Read status register LDB <PTM0+1 * Read timers LDW <PTM0+2 LDW <PTM0+4 PULS D,W,DP RTI ORG $FFFFFFA0 PSHS D,W,DP LDDP #$D0 * Read status register LDB <PTM1+1 * Read timers LDW <PTM1+6 PULS D,W,DP RTI TWI0 EQU $FFFEB000 SPI0 EQU $FFFEC000 PTM0 EQU $FFFED000 PTM1 EQU $FFFED008 ACIA0 EQU $FFFEE000 ACIA1 EQU $FFFEE004 PIA0 EQU $FFFEF000 PIA1 EQU $FFFEF002 PIA2 EQU $FFFEF004 PIA3 EQU $FFFEF006 PIA4 EQU $FFFEF008 * PTM1 interrupt ORG $FFFFFFE8 FDB $FFA0 * PTM0 interrupt ORG $FFFFFFEA FDB $FF80 ORG $FFFFFFF0 FDB $0000 FDB $0000 FDB $0000 FDB $0000 FDB $0000 FDB $0000 FDB $0000 FDB $FF00 END </code></pre></div></div> https://63f09.systella.fr/soc-63f09/programming-examples/article/spi https://63f09.systella.fr/soc-63f09/programming-examples/article/spi 2024-06-17T08:27:32Z text/html en 63F09 <p>``` <span class="caps">ORG</span> $<span class="caps">FFFFFF00</span> <span class="caps">LDMD</span> #$31 <span class="caps">LDS</span> #$<span class="caps">FFFF0000</span> <span class="caps">LDU</span> #$<span class="caps">FFFEF000</span> * Direct mode: address is built with <span class="caps">DS</span>:<span class="caps">DP</span>:8 bits offset <span class="caps">LDDS</span> #$<span class="caps">FFFF</span> <span class="caps">LDDP</span> #$00 * <span class="caps">SPI0</span> * Internal registers: * <span class="caps">SPI0</span>+0: data register * <span class="caps">SPI0</span>+1: control register <br class='autobr' /> * <span class="caps">SPI0</span> control register * Configure divisor (1'000'000) <span class="caps">LDA</span> #%00000001 <span class="caps">STA</span> TX_EMPTY = 1 * <span class="caps">TST</span> Z=0 => TX_EMPTY = 1 * <span class="caps">TST</span> Z=1 => TX_EMPTY = 0 <span class="caps">BEQ</span> <span class="caps">WAIT</span> <span class="caps">RTS</span> <br class='autobr' /> <span class="caps">WAIT2</span>: <span class="caps">LDW</span> #500 <span class="caps">BOUCLE</span>: <span class="caps">DECW</span> <span class="caps">BNE</span> (…)</p> - <a href="https://63f09.systella.fr/soc-63f09/programming-examples/" rel="directory">Programming examples</a> <div class='rss_texte'><div class="precode"><pre class='spip_code spip_code_block' dir='ltr' style='text-align:left;'><code> ORG $FFFFFF00 LDMD #$31 LDS #$FFFF0000 LDU #$FFFEF000 * Direct mode: address is built with DS:DP:8 bits offset LDDS #$FFFF LDDP #$00 * SPI0 * Internal registers: * SPI0+0: data register * SPI0+1: control register * SPI0 control register * Configure divisor (1'000'000) LDA #%00000001 STA <SPI0+1 LDD #5 STD <SPI0 LDA #%00000001 STA <SPI0+1 LDW <SPI0 * Configure SPI0 LDA #%00100000 STA <SPI0+1 * Send data JSR WAIT LDA #$AA STA <SPI0 JSR WAIT LDA #$A5 STA <SPI0 JSR WAIT2 * Abort simulation FCB $CF WAIT: LDB <SPI0+1 ANDB #$40 TSTB * loop while SPI0_CC(TX_EMPTY) = 0 * SPI0_CC and #$40 = #$40 => TX_EMPTY = 1 * TST Z=0 => TX_EMPTY = 1 * TST Z=1 => TX_EMPTY = 0 BEQ WAIT RTS WAIT2: LDW #500 BOUCLE: DECW BNE BOUCLE RTS * IRQ SPI0 ORG $FFFFFF80 * Read SPI RX register to release interrupt request PSHU B LDB <SPI0 PULU B RTI TWI0 EQU $FFFEB000 SPI0 EQU $FFFEC000 PTM0 EQU $FFFED000 PTM1 EQU $FFFED008 ACIA0 EQU $FFFEE000 ACIA1 EQU $FFFEE004 PIA0 EQU $FFFEF000 PIA1 EQU $FFFEF002 PIA2 EQU $FFFEF004 PIA3 EQU $FFFEF006 PIA4 EQU $FFFEF008 * TWI0 interrupt ORG $FFFFFFDA FDB $FF80 ORG $FFFFFFF0 FDB $0000 FDB $0000 FDB $0000 FDB $0000 FDB $0000 FDB $0000 FDB $0000 FDB $0000 END </code></pre></div></div> https://63f09.systella.fr/soc-63f09/programming-examples/article/twi https://63f09.systella.fr/soc-63f09/programming-examples/article/twi 2024-06-14T06:40:13Z text/html en 63F09 <p>Example ``` <span class="caps">ORG</span> $<span class="caps">FFFF0000</span> <span class="caps">LDMD</span> #$31 <span class="caps">LDS</span> #$<span class="caps">FFFE0000</span> <span class="caps">LDU</span> #$<span class="caps">FFFDF000</span> * Direct mode: address is built with <span class="caps">DS</span>:<span class="caps">DP</span>:8 bits offset * i2c controller is at $<span class="caps">FFFEB000</span>-$<span class="caps">FFFEB003</span> <span class="caps">LDDS</span> #$<span class="caps">FFFE</span> <span class="caps">LDDP</span> #$B0 * <span class="caps">TWI0</span> control register <span class="caps">LDA</span> #%00000000 ; polling mode <span class="caps">STA</span> <<span class="caps">TWI0</span>+2 * Set <span class="caps">TWI0</span> clock divisor <span class="caps">LDD</span> #0 <span class="caps">STD</span> <<span class="caps">TWI0</span>+4 * Set slave address <span class="caps">LDD</span> #$50 <span class="caps">STD</span> <<span class="caps">TWI0</span>+6 <br class='autobr' /> * Write into $20 <span class="caps">LDA</span> #$20 <span class="caps">STA</span> (…)</p> - <a href="https://63f09.systella.fr/soc-63f09/programming-examples/" rel="directory">Programming examples</a> <div class='rss_texte'><div class='spip_document_7 spip_document spip_documents spip_document_image spip_documents_center spip_document_center spip_document_avec_legende' data-legende-len="57" data-legende-lenx="x" > <figure class="spip_doc_inner"> <a href='https://63f09.systella.fr/IMG/jpg/i2c.jpg' class="spip_doc_lien mediabox" type="image/jpeg"> <img src='https://63f09.systella.fr/IMG/jpg/i2c.jpg?1718446697' width='500' height='197' alt='' /></a> <figcaption class='spip_doc_legende'> <div class='spip_doc_titre '><strong>i2c transaction with an 24C02 <span class="caps">EEPROM</span> (single and burst) </strong></div> </figcaption></figure> </div><h2 class="spip">Example</h2><div class="precode"><pre class='spip_code spip_code_block' dir='ltr' style='text-align:left;'><code> ORG $FFFF0000 LDMD #$31 LDS #$FFFE0000 LDU #$FFFDF000 * Direct mode: address is built with DS:DP:8 bits offset * i2c controller is at $FFFEB000-$FFFEB003 LDDS #$FFFE LDDP #$B0 * TWI0 control register LDA #%00000000 ; polling mode STA <TWI0+2 * Set TWI0 clock divisor LDD #0 STD <TWI0+4 * Set slave address LDD #$50 STD <TWI0+6 * Write into $20 LDA #$20 STA <TWI0 LDA #%00000001 STA <TWI0+1 LBSR TX_EMPTY ; wait until TX register is loaded in buffer LDA #$4E ; data written at address $20 STA <TWI0 LDA #%00001001 STA <TWI0+1 LDB #%00000011 ; wait until STOP state LBSR POLL * Write into $10 and $11 LDA #$10 STA <TWI0 LDA #%00000001 STA <TWI0+1 LDB #%00010001 ; wait until SLAVE ACK after address LBSR POLL LDA #$3F ; data written at address $10 STA <TWI0 LDA #%00000001 STA <TWI0+1 LDB #%00000101 ; wait until WRITE is started LBSR POLL LDA #$24 ; data written at address $11 STA <TWI0 LDA #%00001001 STA <TWI0+1 LDB #%00000011 ; wait until STOP state LBSR POLL * Read addresses $10 (3F) and $11 (24) LDA #$10 STA <TWI0 * Send data (write mode) LDA #%001 STA <TWI0+1 LDB #%00000101 ; wait until WRITE is started BSR POLL * Receive data (read mode with MACK) LDA #%111 STA <TWI0+1 LDB #%00001000 ; wait until MASTER_ACK state BSR POLL * Wait LDW #$0200 WAIT: DECW BNE WAIT LDF <TWI0 ; read data (#$3F) * TWI0 control register ; IRQ mode LDA #%00100000 STA <TWI0+2 * Receive data (read mode without MACK) LDA #%011 STA <TWI0+1 LDB #%00001001 ; wait until NO_MASTER_ACK state BSR POLL * Read addresses $20 (4E) LDA #$20 STA <TWI0 * Send data (write mode) LDA #%001 STA <TWI0+1 BSR WAIT_ACK * Receive data (read mode without MACK) LDA #%011 STA <TWI0+1 LDB #%00000011 ; wait until STOP state BSR POLL * Read addresses $11 (24) LDA #$11 STA <TWI0 * Send data (write mode) LDA #%001 STA <TWI0+1 BSR WAIT_ACK * Receive data (read mode without MACK) LDA #%011 STA <TWI0+1 LDB #%00000011 ; wait until STOP state BSR POLL ABORT: FCB $CF TX_EMPTY: LDA <TWI0+2 ANDA #$40 BEQ TX_EMPTY RTS WAIT_ACK: LDA <TWI0+2 ANDA #$08 BEQ WAIT_ACK RTS POLL: * Wait for READY state LDA <TWI0+3 CMPR A,B BNE POLL CLR <TWI0 RTS * Interruptions ORG $FFFFFF00 LDE <TWI0 RTI TWI0 EQU $FFFEB000 SPI0 EQU $FFFEC000 PTM0 EQU $FFFED000 PTM1 EQU $FFFED008 ACIA0 EQU $FFFEE000 ACIA1 EQU $FFFEE004 PIA0 EQU $FFFEF000 PIA1 EQU $FFFEF002 PIA2 EQU $FFFEF004 PIA3 EQU $FFFEF006 PIA4 EQU $FFFEF008 * TWI0 interrupt ORG $FFFFFFD8 FDB $FF00 ORG $FFFFFFF0 FDB $0000 FDB $0000 FDB $0000 FDB $0000 FDB $0000 FDB $0000 FDB $0000 FDB $0000 END </code></pre></div></div>