63F09

BAC 63F81

63F09 — 2024-08-23T17:22:19Z

- Peripherals

DMC 63F41

63F09 — 2024-08-23T17:22:01Z

DMC 63F41 is a level-1 direct mapped cache controller. It is not configurable.

Characteristics:

full speed;
direct mapped;
write through;
64 KB of synchronous RAM;
usable in SMP configuration as it contains a cache invalidation subsystem.

RAM 61F512

63F09 — 2024-06-14T06:37:13Z

- Peripherals

ROM 27F512

63F09 — 2024-06-14T06:36:44Z

System on chip contains a 64 Kbytes ROM between $FFFF0000 and $FFFFFFFF. Memory is created with RAM blocks in a read only configuration.

This ROM is hardcoded and initialized with memblcks.rpl.

MMU 63F29

63F09 — 2024-06-14T06:35:58Z

- Peripherals

SPI 63F52

63F09 — 2024-06-14T06:35:26Z

This controller acts as master or slave SPI device.

External signals

MISO
MOSI
SCLK
CS (16 bits)

In slave mode, CS(0) is mandatory SS_n signal. In master mode, CS is used to address slaves's chip select lines. This controller can directly drive 16 SPI slaves or more slave with an additional address decoder.

Internal registers

Registers
Address	Access	7	6	5	4	3	2	1	0
base + 0 when CC(0) = 0	read	RX register
base + 0 when CC(0) = 0	write	TX register
base + 0 when CC(0) = 1	read/write	Clock divisor (MSB)
base + 1	read/write	Control register
base + 1	read/write	BUSY_n/RX data ready	TX empty	RX IRQ enabled	TX IRQ enabled	CPOL	CPHA	Slave SPI	Clock divisor access
base + 1 when CC(0) = 1	read/write	Clock divisor (LSB)
base + 2 when CC(0) = 0	read/write	Chip select register (MSB)
base + 3 when CC(0) = 0	read/write	Chip select register (LSB)

Notes

Please note that CS(0) is only used to read or write clock divisor register. This bit returns to 0 after first access to clock register (LSB). Chip select register cannot be selected when CS(0) = 1 (write operation is ignored and read operation always returns $00).

TWI (i2c) 63F54

63F09 — 2024-06-14T06:35:04Z

Internal registers

Registers
Address	Access	7	6	5	4	3	2	1	0
base + 0	read	RX register
base + 0	write	TX register
base + 1	read	Current start register (cleared when transaction begins)
	write	Start register
	write	DC [1]	DC	DC	soft reset	stop after slave's ack	master ack	read/not write	start request
base + 2	read/write	Control register
base + 2	read/write	RX data ready	TX empty	RX IRQ enabled	TX IRQ enabled	ACK received	ACK error	busy	10 bits address
base + 3	read	Status register
		READY (00000001)
		READY (00000001)
		START (00000010)
		STOP (00000011)
		READ (00000100)
		WRITE (00000101)
		MASTER ACK (00001000)
		NO MASTER ACK (00001001)
		SLAVE ACK after address (00010000)
		SLAVE ACK after data (00010001)
		ERROR (10000000)
base + 3	write	DC	DC	DC	DC	DC	DC	DC	DC
base + 4	read/write	Clock divisor (MSB)
base + 5	read/write	Clock divisor (LSB)
base + 6	read/write	Slave address (MSB)
base + 7	read/write	Slave address (LSB)

[1] Don't care

PTM 63F40

63F09 — 2024-06-14T06:34:25Z

This programmable timer has been designed to be compatible with regular MC6840.

- Peripherals

PIA 63F21

63F09 — 2024-06-14T06:34:02Z

This component runs as a regular MC6821. Please note that 63F21 only contains half MC6821.

- Peripherals

ACIA 63F50

63F09 — 2024-06-14T06:33:42Z

This asynchronous serial interface has been designed to be compatible with regular MC6850.

- Peripherals