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	<title>63F09</title>
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		<title>63F09</title>
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<item xml:lang="en">
		<title>Opcodes</title>
		<link>https://63f09.systella.fr/cpu-63f09/article/opcodes</link>
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		<dc:date>2024-05-28T12:25:30Z</dc:date>
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		<dc:creator>63F09</dc:creator>



		<description>
&lt;p&gt;Warning: in 63F09 mode (32 bits), there is no 0 or Z (zero) register. Nevertheless, in 6309 mode (16 bits), Z is usable with &lt;span class=&#034;caps&#034;&gt;EXG&lt;/span&gt; and &lt;span class=&#034;caps&#034;&gt;TFR&lt;/span&gt; opcodes. &lt;br class='autobr' /&gt;
In 63F09 mode, &lt;span class=&#034;caps&#034;&gt;EXG&lt;/span&gt; and &lt;span class=&#034;caps&#034;&gt;TFR&lt;/span&gt; operands are modified to exchange or transfer new Q and &lt;span class=&#034;caps&#034;&gt;DS&lt;/span&gt; registers. ______________________________________
&lt;br class='autobr' /&gt;
| 0E &lt;span class=&#034;caps&#034;&gt;JMP&lt;/span&gt; Dir&lt;/p&gt;


-
&lt;a href="https://63f09.systella.fr/cpu-63f09/" rel="directory"&gt;CPU 63F09&lt;/a&gt;


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 <content:encoded>&lt;div class='rss_texte'&gt;&lt;p&gt;Warning: in 63F09 mode (32 bits), there is no 0 or Z (zero) register. Nevertheless, in 6309 mode (16 bits), Z is usable with &lt;span class=&#034;caps&#034;&gt;EXG&lt;/span&gt; and &lt;span class=&#034;caps&#034;&gt;TFR&lt;/span&gt; opcodes.&lt;/p&gt;
&lt;p&gt;In 63F09 mode, &lt;span class=&#034;caps&#034;&gt;EXG&lt;/span&gt; and &lt;span class=&#034;caps&#034;&gt;TFR&lt;/span&gt; operands are modified to exchange or transfer new Q and &lt;span class=&#034;caps&#034;&gt;DS&lt;/span&gt; registers.&lt;/p&gt;
&lt;div class=&#034;precode&#034;&gt;&lt;pre class='spip_code spip_code_block' dir='ltr' style='text-align:left;'&gt;&lt;code&gt; ______________________________________ | | | Opcode Mnemonic Mode | | (* 6309) | | (# 63F09) | | (% 6309 only) | |--------------------------------------| | 00 NEG Direct | | * 01 OIM Direct | | * 02 AIM Direct | | 03 COM Direct | | 04 LSR Direct | | * 05 EIM Direct | | 06 ROR Direct | | 07 ASR Direct | | 08 ASL/LSL Direct | | 09 ROL Direct | | 0A DEC Direct | | * 0B TIM Direct | | 0C INC Direct | | 0D TST Direct | | 0E JMP Direct | | 0F CLR Direct | -------------------------------------- -------------------------------------- | 10 (PREBYTE) | | 11 (PREBYTE) | | 12 NOP Inherent | | 13 SYNC Inherent | | * 14 SEXW Inherent | | 15 HCF | | 16 LBRA Relative | | 17 LBSR Relative | | 18 (PREBYTE FPU) | | 19 DAA Inherent | | 1A ORCC Immediate | | 1B (PREBYTE) | | 1C ANDCC Immediate | | 1D SEX Inherent | | 1E EXG Immediate | | 1F TFR Immediate | -------------------------------------- -------------------------------------- | 20 BRA Relative | | 21 BRN Relative | | 22 BHI Relative | | 23 BLS Relative | | 24 BHS/BCC Relative | | 25 BLO/BCS Relative | | 26 BNE Relative | | 27 BEQ Relative | | 28 BVC Relative | | 29 BVS Relative | | 2A BPL Relative | | 2B BMI Relative | | 2C BGE Relative | | 2D BLT Relative | | 2E BGT Relative | | 2F BLE Relative | -------------------------------------- -------------------------------------- | 30 LEAX Indexed | | 31 LEAY Indexed | | 32 LEAS Indexed | | 33 LEAU Indexed | | 34 PSHS Immediate | | 35 PULS Immediate | | 36 PSHU Immediate | | 37 PULU Immediate | | # 38 ENI Inherent | unmask all interrupts | 39 RTS Inherent | | 3A ABX Inherent | | 3B RTI Inherent | | 3C CWAI Immediate | mask in 8 bits for 6809/6309, 32 bits for 63F09. | 3D MUL Inherent | | # 3E DII Inherent | mask all interrupts | 3F SWI Inherent | -------------------------------------- -------------------------------------- | 40 NEGA Inherent | | # 41 LOCK Inherent | | 42 | | 43 COMA Inherent | | 44 LSRA Inherent | | 45 | | 46 RORA Inherent | | 47 ASRA Inherent | | 48 ASLA/LSLA Inherent | | 49 ROLA Inherent | | 4A DECA Inherent | | 4B | | 4C INCA Inherent | | 4D TSTA Inherent | | 4E | | 4F CLRA Inherent | -------------------------------------- -------------------------------------- | 50 NEGB Inherent | | # 51 UNLOCK Inherent | | 52 | | 53 COMB Inherent | | 54 LSRB Inherent | | 55 | | 56 RORB Inherent | | 57 ASRB Inherent | | 58 ASLB/LSLB Inherent | | 59 ROLB Inherent | | 5A DECB Inherent | | 5B | | 5C INCB Inherent | | 5D TSTB Inherent | | 5E | | 5F CLRB Inherent | -------------------------------------- -------------------------------------- | 60 NEG Indexed | | * 61 OIM Indexed | | * 62 AIM Indexed | | 63 COM Indexed | | 64 LSR Indexed | | * 65 EIM Indexed | | 66 ROR Indexed | | 67 ASR Indexed | | 68 ASL/LSL Indexed | | 69 ROL Indexed | | 6A DEC Indexed | | * 6B TIM Indexed | | 6C INC Indexed | | 6D TST Indexed | | 6E JMP Indexed | | 6F CLR Indexed | -------------------------------------- -------------------------------------- | 70 NEG Extended | | * 71 OIM Extended | | * 72 AIM Extended | | 73 COM Extended | | 74 LSR Extended | | * 75 EIM Extended | | 76 ROR Extended | | 77 ASR Extended | | 78 ASL/LSL Extended | | 79 ROL Extended | | 7A DEC Extended | | * 7B TIM Extended | | 7C INC Extended | | 7D TST Extended | | 7E JMP Extended | | 7F CLR Extended | -------------------------------------- -------------------------------------- | 80 SUBA Immediate | | 81 CMPA Immediate | | 82 SBCA Immediate | | 83 SUBD Immediate | | 84 ANDA Immediate | | 85 BITA Immediate | | 86 LDA Immediate | | 87 | | 88 EORA Immediate | | 89 ADCA Immediate | | 8A ORA Immediate | | 8B ADDA Immediate | | 8C CMPX Immediate | | 8D BSR Relative | | 8E LDX Immediate | | 8F | -------------------------------------- -------------------------------------- | 90 SUBA Direct | | 91 CMPA Direct | | 92 SBCA Direct | | 93 SUBD Direct | | 94 ANDA Direct | | 95 BITA Direct | | 96 LDA Direct | | 97 STA Direct | | 98 EORA Direct | | 99 ADCA Direct | | 9A ORA Direct | | 9B ADDA Direct | | 9C CMPX Direct | | 9D JSR Direct | | 9E LDX Direct | | 9F STX Direct | -------------------------------------- -------------------------------------- | A0 SUBA Indexed | | A1 CMPA Indexed | | A2 SBCA Indexed | | A3 SUBD Indexed | | A4 ANDA Indexed | | A5 BITA Indexed | | A6 LDA Indexed | | A7 STA Indexed | | A8 EORA Indexed | | A9 ADCA Indexed | | AA ORA Indexed | | AB ADDA Indexed | | AC CMPX Indexed | | AD JSR Indexed | | AE LDX Indexed | | AF STX Indexed | -------------------------------------- -------------------------------------- | B0 SUBA Extended | | B1 CMPA Extended | | B2 SBCA Extended | | B3 SUBD Extended | | B4 ANDA Extended | | B5 BITA Extended | | B6 LDA Extended | | B7 STA Extended | | B8 EORA Extended | | B9 ADCA Extended | | BA ORA Extended | | BB ADDA Extended | | BC CMPX Extended | | BD JSR Extended | | BE LDX Extended | | BF STX Extended | -------------------------------------- -------------------------------------- | C0 SUBB Immediate | | C1 CMPB Immediate | | C2 SBCB Immediate | | C3 ADDD Immediate | | C4 ANDB Immediate | | C5 BITB Immediate | | C6 LDB Immediate | | C7 | | C8 EORB Immediate | | C9 ADCB Immediate | | CA ORB Immediate | | CB ADDB Immediate | | CC LDD Immediate | | * CD LDQ Immediate | | CE LDU Immediate | | CF | -------------------------------------- -------------------------------------- | D0 SUBB Direct | | D1 CMPB Direct | | D2 SBCB Direct | | D3 ADDD Direct | | D4 ANDB Direct | | D5 BITB Direct | | D6 LDB Direct | | D7 STB Direct | | D8 EORB Direct | | D9 ADCB Direct | | DA ORB Direct | | DB ADDB Direct | | DC LDD Direct | | DD STD Direct | | DE LDU Direct | | DF STU Direct | -------------------------------------- -------------------------------------- | E0 SUBB Indexed | | E1 CMPB Indexed | | E2 SBCB Indexed | | E3 ADDD Indexed | | E4 ANDB Indexed | | E5 BITB Indexed | | E6 LDB Indexed | | E7 STB Indexed | | E8 EORB Indexed | | E9 ADCB Indexed | | EA ORB Indexed | | EB ADDB Indexed | | EC LDD Indexed | | ED STD Indexed | | EE LDU Indexed | | EF STU Indexed | -------------------------------------- -------------------------------------- | F0 SUBB Extended | | F1 CMPB Extended | | F2 SBCB Extended | | F3 ADDD Extended | | F4 ANDB Extended | | F5 BITB Extended | | F6 LDB Extended | | F7 STB Extended | | F8 EORB Extended | | F9 ADCB Extended | | FA ORB Extended | | FB ADDB Extended | | FC LDD Extended | | FD STD Extended | | FE LDU Extended | | FF STU Extended | -------------------------------------- -------------------------------------- | 1020 | | 1021 LBRN Relative | | 1022 LBHI Relative | | 1023 LBLS Relative | | 1024 LBHS/LBCC Relative | | 1025 LBCS/LBLO Relative | | 1026 LBNE Relative | | 1027 LBEQ Relative | | 1028 LBVC Relative | | 1029 LBVS Relative | | 102A LBPL Relative | | 102B LBMI Relative | | 102C LBGE Relative | | 102D LBLT Relative | | 102E LBGT Relative | | 102F LBLE Relative | -------------------------------------- -------------------------------------- | * 1030 ADDR Register | | * 1031 ADCR Register | | * 1032 SUBR Register | | * 1033 SBCR Register | | * 1034 ANDR Register | | * 1035 ORR Register | | * 1036 EORR Register | | * 1037 CMPR Register | | % 1038 PSHSW Inherent | | % 1039 PULSW Inherent | | % 103A PSHUW Inherent | | % 103B PULUW Inherent | | 103C | | 103D | | 103E | | 103F SWI2 Inherent | -------------------------------------- -------------------------------------- | * 1040 NEGD Inherent | | # 1041 ANDW Immediate | | # 1042 ORW Immediate | | * 1043 COMD Inherent | | * 1044 LSRD Inherent | | # 1045 EORW Immediate | | * 1046 RORD Inherent | | * 1047 ASRD Inherent | | * 1048 ASLD/LSLD Inherent | | * 1049 ROLD Inherent | | * 104A DECD Inherent | | # 104B ADCW Immediate | | * 104C INCD Inherent | | * 104D TSTD Inherent | | # 104E SBCW Immediate | | * 104F CLRD Inherent | -------------------------------------- -------------------------------------- | # 1050 NEGW Inherent | | # 1051 ANDW Direct | | # 1052 ORW Direct | | * 1053 COMW Inherent | | * 1054 LSRW Inherent | | # 1055 EORW Direct | | * 1056 RORW Inherent | | # 1057 ASRW Inherent | | # 1058 ASLW/LSLW Inherent | | * 1059 ROLW Inherent | | * 105A DECW Inherent | | # 105B ADCW Direct | | * 105C INCW Inherent | | * 105D TSTW Inherent | | # 105E SBCW Direct | | * 105F CLRW Inherent | -------------------------------------- -------------------------------------- | # 1060 NEGQ Inherent | | # 1061 ANDW Indexed | | # 1062 ORW Indexed | | # 1063 COMQ Inherent | | # 1064 LSRQ Inherent | | # 1065 EORW Indexed | | # 1066 RORQ Inherent | | # 1067 ASRQ Inherent | | # 1068 ASLQ/LSLQ Inherent | | # 1069 ROLQ Inherent | | # 106A DECQ Inherent | | # 106B ADCW Indexed | | # 106C INCQ Inherent | | # 106D TSTQ Inherent | | # 106E SBCW Indexed | | # 106F CLRQ Inherent | -------------------------------------- -------------------------------------- | # 1070 NEGV Inherent | | # 1071 ANDW Extended | | # 1072 ORW Extended | | # 1073 COMV Inherent | | # 1074 LSRV Inherent | | # 1075 EORW Extended | | # 1076 RORV Inherent | | # 1077 ASRV Inherent | | # 1078 ASLV/LSLV Inherent | | # 1079 ROLV Inherent | | # 107A DECV Inherent | | # 107B ADCW Extended | | # 107C INCV Inherent | | # 107D TSTV Inherent | | # 107E SBCW Extended | | # 107F CLRV Inherent | -------------------------------------- -------------------------------------- | * 1080 SUBW Immediate | | * 1081 CMPW Immediate | | * 1082 SBCD Immediate | | 1083 CMPD Immediate | | * 1084 ANDD Immediate | | * 1085 BITD Immediate | | * 1086 LDW Immediate | | 1087 | | * 1088 EORD Immediate | | * 1089 ADCD Immediate | | * 108A ORD Immediate | | * 108B ADDW Immediate | | 108C CMPY Immediate | | # 108D BITW Immediate | | 108E LDY Immediate | | 108F | -------------------------------------- -------------------------------------- | * 1090 SUBW Direct | | * 1091 CMPW Direct | | * 1092 SBCD Direct | | 1093 CMPD Direct | | * 1094 ANDD Direct | | * 1095 BITD Direct | | * 1096 LDW Direct | | * 1097 STW Direct | | * 1098 EORD Direct | | * 1099 ADCD Direct | | * 109A ORD Direct | | * 109B ADDW Direct | | 109C CMPY Direct | | 109D BITW Direct | | 109E LDY Direct | | 109F STY Direct | -------------------------------------- -------------------------------------- | * 10A0 SUBW Indexed | | * 10A1 CMPW Indexed | | * 10A2 SBCD Indexed | | 10A3 CMPD Indexed | | * 10A4 ANDD Indexed | | * 10A5 BITD Indexed | | * 10A6 LDW Indexed | | * 10A7 STW Indexed | | * 10A8 EORD Indexed | | * 10A9 ADCD Indexed | | * 10AA ORD Indexed | | * 10AB ADDW Indexed | | 10AC CMPY Indexed | | # 10AD BITW Indexed | | 10AE LDY Indexed | | 10AF STY Indexed | -------------------------------------- -------------------------------------- | * 10B0 SUBW Extended | | * 10B1 CMPW Extended | | * 10B2 SBCD Extended | | 10B3 CMPD Extended | | * 10B4 ANDD Extended | | * 10B5 BITD Extended | | * 10B6 LDW Extended | | * 10B7 STW Extended | | * 10B8 EORD Extended | | * 10B9 ADCD Extended | | * 10BA ORD Extended | | * 10BB ADDW Extended | | 10BC CMPY Extended | | # 10BD BITW Extended | | 10BE LDY Extended | | 10BF STY Extended | -------------------------------------- -------------------------------------- | # 10C0 ANDQ Immediate | | # 10C1 BITQ Immediate | | # 10C2 EORQ Immediate | | # 10C3 ORQ Immediate | | # 10C6 LDDP Immediate | | # 10C8 LDDS Immediate | | # 10CA LDV Immediate | | 10CE LDS Immediate | -------------------------------------- -------------------------------------- | # 10D0 ANDQ Direct | | # 10D1 BITQ Direct | | # 10D2 EORQ Direct | | # 10D3 ORQ Direct | | # 10D6 LDDP Direct | | # 10D7 STDP Direct | | # 10D8 LDDS Direct | | # 10D9 STDS Direct | | # 10DA LDV Direct | | # 10DB STV Direct | | * 10DC LDQ Direct | | * 10DD STQ Direct | | 10DE LDS Direct | | 10DF STS Direct | -------------------------------------- -------------------------------------- | # 10E0 ANDQ Indexed | | # 10E1 BITQ Indexed | | # 10E2 EORQ Indexed | | # 10E3 ORQ Indexed | | # 10E6 LDDP Indexed | | # 10E7 STDP Indexed | | # 10E8 LDDS Indexed | | # 10E9 STDS Indexed | | # 10EA LDV Indexed | | # 10EB STV Indexed | | * 10EC LDQ Indexed | | * 10ED STQ Indexed | | 10EE LDS Indexed | | 10EF STS Indexed | -------------------------------------- -------------------------------------- | # 10F0 ANDQ Extended | | # 10F1 BITQ Extended | | # 10F2 EORQ Extended | | # 10F3 ORQ Extended | | # 10F6 LDDP Extended | | # 10F7 STDP Extended | | # 10F8 LDDS Extended | | # 10F9 STDS Extended | | # 10FA LDV Extended | | # 10FB STV Extended | | * 10FC LDQ Extended | | * 10FD STQ Extended | | 10FE LDS Extended | | 10FF STS Extended | -------------------------------------- -------------------------------------- | * 1130 BAND Memory | | * 1131 BIAND Memory | | * 1132 BOR Memory | | * 1133 BIOR Memory | | * 1134 BEOR Memory | | * 1135 BIEOR Memory | | * 1136 LDBT Memory | | * 1137 STBT Memory | | * 1138 TFM R+,R+ Register | | * 1139 TFM R-,R- Register | | * 113A TFM R+,R Register | | * 113B TFM R,R+ Register | | * 113C BITMD Immediate | | * 113D LDMD Immediate | | 113E | | 113F SWI3 Inherent | -------------------------------------- -------------------------------------- | # 1140 NEGE Inherent | | # 1141 ADDV Immediate | | # 1142 SUBV Immediate | | * 1143 COME Inherent | | # 1144 LSRE Inherent | | # 1145 CMPV Immediate | | # 1146 RORE Inherent | | # 1147 ASRE Inherent | | # 1148 ASLE/LSLE Inherent | | # 1149 ROLE Inherent | | * 114A DECE Inherent | | # 114B ADCV Immediate | | * 114C INCE Inherent | | * 114D TSTE Inherent | | # 114E SBCV Immediate | | * 114F CLRE Inherent | -------------------------------------- -------------------------------------- | # 1150 NEGF Inherent | | # 1151 ADDV Direct | | # 1152 SUBV Direct | | * 1153 COMF Inherent | | # 1154 LSRF Inherent | | # 1155 CMPV Direct | | # 1156 RORF Inherent | | # 1157 ASRF Inherent | | # 1158 ASLF/LSLF Inherent | | # 1159 ROLF Inherent | | * 115A DECF Inherent | | # 115B ADCV Direct | | * 115C INCF Inherent | | * 115D TSTF Inherent | | # 115E SBCV Direct | | * 115F CLRF Inherent | -------------------------------------- -------------------------------------- | # 1161 ADDV Indexed | | # 1162 SUBV Indexed | | # 1165 CMPV Indexed | | # 116B ADCV Indexed | | # 116E SBCV Indexed | -------------------------------------- -------------------------------------- | # 1171 ADDV Extended | | # 1172 SUBV Extended | | # 1175 CMPV Extended | | # 117B ADCV Extended | | # 117E SBCV Extended | -------------------------------------- -------------------------------------- | * 1180 SUBE Immediate | | * 1181 CMPE Immediate | | # 1182 SBCE Immediate | | 1183 CMPU Immediate | | # 1184 ANDE Immediate | | # 1185 BITE Immediate | | * 1186 LDE Immediate | | 1187 | | # 1188 EORE Immediate | | # 1189 ADCE Immediate | | # 118A ORE Immediate | | * 118B ADDE Immediate | | 118C CMPS Immediate | | * 118D DIVD Immediate | | * 118E DIVQ Immediate | | * 118F MULD Immediate | -------------------------------------- -------------------------------------- | * 1190 SUBE Direct | | * 1191 CMPE Direct | | # 1192 SBCE Direct | | 1193 CMPU Direct | | # 1194 ANDE Direct | | # 1195 BITE Direct | | * 1196 LDE Direct | | * 1197 STE Direct | | # 1198 EORE Direct | | # 1199 ADCE Direct | | # 119A ORE Direct | | * 119B ADDE Direct | | 119C CMPS Direct | | * 119D DIVD Direct | | * 119E DIVQ Direct | | * 119F MULD Direct | -------------------------------------- -------------------------------------- | * 11A0 SUBE Indexed | | * 11A1 CMPE Indexed | | # 11A2 SBCE Indexed | | 11A3 CMPU Indexed | | # 11A4 ANDE Indexed | | # 11A5 BITE Indexed | | * 11A6 LDE Indexed | | * 11A7 STE Indexed | | # 11A8 EORE Indexed | | # 11A9 ADCE Indexed | | # 11AA ORE Indexed | | * 11AB ADDE Indexed | | 11AC CMPS Indexed | | * 11AD DIVD Indexed | | * 11AE DIVQ Indexed | | * 11AF MULD Indexed | -------------------------------------- -------------------------------------- | * 11B0 SUBE Extended | | * 11B1 CMPE Extended | | # 11B2 SBCE Extended | | 11B3 CMPU Extended | | # 11B4 ANDE Extended | | # 11B5 BITE Extended | | * 11B6 LDE Extended | | * 11B7 STE Extended | | # 11B8 EORE Extended | | # 11B9 ADCE Extended | | # 11BA ORE Extended | | * 11BB ADDE Extended | | 11BC CMPS Extended | | * 11BD DIVD Extended | | * 11BE DIVQ Extended | | * 11BF MULD Extended | -------------------------------------- -------------------------------------- | * 11C0 SUBF Immediate | | * 11C1 CMPF Immediate | | # 11C2 SBCF Immediate | | # 11C3 SUBQ Immediate | | # 11C4 ANDF Immediate | | # 11C5 BITF Immediate | | * 11C6 LDF Immediate | | # 11C7 | | # 11C8 EORF Immediate | | # 11C9 ADCF Immediate | | # 11CA ORF Immediate | | * 11CB ADDF Immediate | | # 11CC SBCQ Immediate | | # 11CD DIVDU Immediate | | # 11CE DIVQU Immediate | | # 11CF MULDU Immediate | -------------------------------------- -------------------------------------- | * 11D0 SUBF Direct | | * 11D1 CMPF Direct | | # 11D2 SBCF Direct | | # 11D3 SUBQ Direct | | # 11D4 ANDF Direct | | # 11D5 BITF Direct | | * 11D6 LDF Direct | | * 11D7 STF Direct | | # 11D8 EORF Direct | | # 11D9 ADCF Direct | | # 11DA ORF Direct | | * 11DB ADDF Direct | | # 11DC SBCQ Direct | | # 11DD DIVDU Direct | | # 11DE DIVQU Direct | | # 11DF MULDU Direct | -------------------------------------- -------------------------------------- | * 11E0 SUBF Indexed | | * 11E1 CMPF Indexed | | # 11E2 SBCF Indexed | | # 11E3 SUBQ Indexed | | # 11E4 ANDF Indexed | | # 11E5 BITF Indexed | | * 11E6 LDF Indexed | | * 11E7 STF Indexed | | # 11E8 EORF Indexed | | # 11E9 ADCF Indexed | | # 11EA ORF Indexed | | * 11EB ADDF Indexed | | # 11EC SBCQ Indexed | | # 11ED DIVDU Indexed | | # 11EE DIVQU Indexed | | # 11EF MULDU Indexed | -------------------------------------- -------------------------------------- | * 11F0 SUBF Extended | | * 11F1 CMPF Extended | | # 11F2 SBCF Extended | | # 11F3 SUBQ Extended | | # 11F4 ANDF Extended | | # 11F5 BITF Extended | | * 11F6 LDF Extended | | * 11F7 STF Extended | | # 11F8 EORF Extended | | # 11F9 ADCF Extended | | # 11FA ORF Extended | | * 11FB ADDF Extended | | # 11FC SBCQ Extended | | # 11FD DIVDU Extended | | # 11FE DIVQU Extended | | # 11FF MULDU Extended | -------------------------------------- -------------------------------------- | # 1B40 NEGO Inherent | | # 1B41 | | # 1B42 | | # 1B43 COMO Inherent | | # 1B44 LSRO Inherent | | # 1B45 | | # 1B46 RORO Inherent | | # 1B47 ASRO Inherent | | # 1B48 ASLO/LSLO Inherent | | # 1B49 ROLO Inherent | | # 1B4A DECO Inherent | | # 1B4B | | # 1B4C INCO Inherent | | # 1B4D TSTO Inherent | | # 1B4E SEXV Inherent | | # 1B4F CLRO Inherent | -------------------------------------- -------------------------------------- | # 1B80 SUBO Immediate | | # 1B81 CMPO Immediate | | # 1B82 SBCO Immediate | | | | # 1B84 ANDO Immediate | | # 1B85 BITO Immediate | | # 1B86 LDO Immediate | | | | # 1B88 EORO Immediate | | # 1B89 ADCO Immediate | | # 1B8A ORO Immediate | | # 1B8B ADDO Immediate | | # 1B8C MULQ Immediate | | # 1B8D DIVO Immediate | | # 1B8E DIVOU Immediate | | # 1B8F MULQU Immediate | -------------------------------------- -------------------------------------- | # 1B90 SUBO Direct | | # 1B91 CMPO Direct | | # 1B92 SBCO Direct | | | | # 1B94 ANDO Direct | | # 1B95 BITO Direct | | # 1B96 LDO Direct | | # 1B97 STO Direct | | # 1B98 EORO Direct | | # 1B99 ADCO Direct | | # 1B9A ORO Direct | | # 1B9B ADDO Direct | | # 1B9C MULQ Direct | | # 1B9D DIVO Direct | | # 1B9E DIVOU Direct | | # 1B9F MULQU Direct | -------------------------------------- -------------------------------------- | # 1BA0 SUBO Indexed | | # 1BA1 CMPO Indexed | | # 1BA2 SBCO Indexed | | | # 1BA4 ANDO Indexed | | # 1BA5 BITO Indexed | | # 1BA6 LDO Indexed | | # 1BA7 STO Indexed | | # 1BA8 EORO Indexed | | # 1BA9 ADCO Indexed | | # 1BAA ORO Indexed | | # 1BAB ADDO Indexed | | # 1BAC MULQ Indexed | | # 1BAD DIVO Indexed | | # 1BAE DIVOU Indexed | | # 1BAF MULQU Indexed | -------------------------------------- -------------------------------------- | # 1BB0 SUBO Extended | | # 1BB1 CMPO Extended | | # 1BB2 SBCO Extended | | | | # 1BB4 ANDO Extended | | # 1BB5 BITO Extended | | # 1BB6 LDO Extended | | # 1BB7 STO Extended | | # 1BB8 EORO Extended | | # 1BB9 ADCO Extended | | # 1BBA ORO Extended | | # 1BBB ADDO Extended | | # 1BBC MULQ Extended | | # 1BBD DIVO Extended | | # 1BBE DIVOU Extended | | # 1BBF MULQU Extended | -------------------------------------- -------------------------------------- | # 1BC0 ANDV Immediate | | # 1BC1 BITV Immediate | | # 1BC2 EORV Immediate | | # 1BC3 ORV Immediate | | # 1BC8 MULOU Immediate | | # 1BC9 MULO Immediate | | # 1BCD ADCQ Immediate | | # 1BCE CMPQ Immediate | | # 1BCF ADDQ Immediate | -------------------------------------- -------------------------------------- | # 1BD0 ANDV Direct | | # 1BD1 BITV Direct | | # 1BD2 EORV Direct | | # 1BD3 ORV Direct | | # 1BD8 MULOU Direct | | # 1BD9 MULO Direct | | # 1BDD ADCQ Direct | | # 1BDE CMPQ Direct | | # 1BDF ADDQ Direct | -------------------------------------- -------------------------------------- | # 1BE0 ANDV Indexed | | # 1BE1 BITV Indexed | | # 1BE2 EORV Indexed | | # 1BE3 ORV Indexed | | # 1BE8 MULOU Indexed | | # 1BE9 MULO Indexed | | # 1BED ADCQ Indexed | | # 1BEE CMPQ Indexed | | # 1BEF ADDQ Indexed | -------------------------------------- -------------------------------------- | # 1BF0 ANDV Extended | | # 1BF1 BITV Extended | | # 1BF2 EORV Extended | | # 1BF3 ORV Extended | | # 1BF8 MULOU Extended | | # 1BF9 MULO Extended | | # 1BFD ADCQ Extended | | # 1BFE CMPQ Extended | | # 1BFF ADDQ Extended | -------------------------------------- FPU contains 16 registers (64 bits) from FP1 to FP16 on a stack and can handle 32 or 64 bits float values. LD/ST pushes or pulls 32 or 64 binary data on level 1. Stack manipulation are the same instructions used in RPL : dup, dup2, dupn, drop, drop2, dropn, pick, over, rot, roll, rolld. -------------------------------------- | # 1800 SETRNE Immediate | | # 1801 SETRTZ Immediate | | # 1802 SETRDN Immediate | | # 1803 SETRUP Immediate | | # 1804 SETRMM Immediate | | # 1805 SETDYN Immediate | -------------------------------------- -------------------------------------- | # 1810 PSHSFP Immediate | | # 1811 PSHUFP Immediate | | # 1812 PULSFP Immediate | | # 1813 PULUFP Immediate | | # 1814 TFROFP Immediate | DUP stack and transfer O to FP1 | # 1815 TFRFPO Immediate | Tranfer FP1 to O and DROP stack -------------------------------------- -------------------------------------- | # 1820 BNV Relative | Invalid | # 1821 BDZ Relative | Division by zero | # 1822 BOV Relative | Overflow | # 1823 BUN Relative | Underflow | # 1824 BIX Relative | Inexact | # 1825 BFT Relative | Branch if float result is true | # 1826 BFF Relative | Branch if float result is false | # 1828 LBNV Relative | | # 1829 LBDZ Relative | | # 182A LBOV Relative | | # 182B LBUN Relative | | # 182C LBIX Relative | | # 182D LBFT Relative | | # 182E LBFF Relative | -------------------------------------- -------------------------------------- | # 1834 CVTOI2D Inherent | Convert signed integer (64 bits) to double | # 1835 CVTOU2D Inherent | Convert unsigned integer (64 bits) to double | # 1836 CVTOI2S Inherent | Convert signed integer (64 bits) to float | # 1837 CVTOU2S Inherent | Convert unsigned integer (64 bits) to float | # 1838 CVTS2OI Inherent | Convert float to signed integer (64 bits) | # 1839 CVTS2OU Inherent | Convert float to unsigned integer (64 bits) | # 183A CVTD2OI Inherent | Convert double to signed integer (64 bits) | # 183B CVTD2OU Inherent | Convert double to unsigned integer (64 bits) -------------------------------------- -------------------------------------- | # 1880 LDSFP Immediate | Load FP1 (32 bits) | # 1881 LDDFP Immediate | Load FP1 (64 bits) -------------------------------------- -------------------------------------- | # 1890 LDSFP Direct | | # 1891 LDDFP Direct | | # 1892 STSFP Direct | Store FP1 (32 bits) | # 1893 STDFP Direct | Store FP1 (64 bits) -------------------------------------- -------------------------------------- | # 18A0 LDSFP Indexed | | # 18A1 LDDFP Indexed | | # 18A2 STSFP Indexed | | # 18A3 STDFP Indexed | -------------------------------------- -------------------------------------- | # 18B0 LDSFP Extended | | # 18B1 LDDFP Extended | | # 18B2 STSFP Extended | | # 18B3 STDFP Extended | -------------------------------------- -------------------------------------- | # 18C0 CVTD2S Inherent | Convert double to float | # 18C1 CVTS2D Inherent | Convert float to double | # 18C4 CVTI2D Inherent | Convert signed integer (32 bits) to double | # 18C5 CVTU2D Inherent | Convert unsigned integer (32 bits) to double | # 18C6 CVTI2S Inherent | Convert signed integer (32 bits) to float | # 18C7 CVTU2S Inherent | Convert unsigned integer (32 bits) to float | # 18C8 CVTS2I Inherent | Convert float to signed integer (32 bits) | # 18C9 CVTS2U Inherent | Convert float to unsigned integer (32 bits) | # 18CA CVTD2I Inherent | Convert double to signed integer (32 bits) | # 18CB CVTD2U Inherent | Convert double to unsigned integer (32 bits) -------------------------------------- -------------------------------------- | # 18D0 DROPFP Inherent | | # 18D1 DROP2FP Inherent | | # 18D2 DUPFP Inherent | | # 18D3 DUP2FP Inherent | | # 18D4 SWAPFP Inherent | | # 18D5 OVERFP Inherent | | # 18D6 ROTFP Inherent | | # 18D7 DUPNFP Immediate | | # 18D8 DROPNFP Immediate | | # 18D9 ROLLFP Immediate | | # 18DA ROLLDFP Immediate | | # 18DB PICKFP Immediate | | # 18DC CLRFP Inherent | -------------------------------------- +, -, *, / : FP2 operation FP1 FSGNJ FP2 with sign of FP1 FMADDS : FP3 * FP2 + FP1 FMSUBS : FP3 * FP2 - FP1 FNMADDS : - FP3 * FP2 + FP1 FNMSUBS : - FP3 * FP2 - FP1 FCMP returns result in FP1, not in FPU flags register. FCMP called with SETRDN : equal FCMP called with SETRTZ : less than FCMP called with SETRNE : less or equal FCLASS : Bit 0 rs1 is -inf. Bit 1 rs1 is a negative normal number. Bit 2 rs1 is a negative subnormal number. Bit 3 rs1 is -0. Bit 4 rs1 is +0. Bit 5 rs1 is a positive subnormal number. Bit 6 rs1 is a positive normal number. Bit 7 rs1 is +inf Bit 8 rs1 is a signaling NaN. Bit 9 rs1 is a quiet NaN. &lt;= No mathematical exception -------------------------------------- | # 18E0 FMADDS Inherent | | # 18E1 FMSUBS Inherent | | # 18E2 FNMADDS Inherent | | # 18E3 FNMSUBS Inherent | | # 18E4 FADDS Inherent | | # 18E5 FSUBS Inherent | | # 18E6 FMULS Inherent | | # 18E7 FDIVS Inherent | | # 18E8 FSQRTS Inherent | | # 18E9 FSNGJS Inherent | | # 18EA FCMPS Inherent | | # 18EB FMAXS Inherent | | # 18EC FCLASSS Inherent | -------------------------------------- -------------------------------------- | # 18F0 FMADDD Inherent | | # 18F1 FMSUBD Inherent | | # 18F2 FNMADDD Inherent | | # 18F3 FNMSUBD Inherent | | # 18F4 FADDD Inherent | | # 18F5 FSUBD Inherent | | # 18F6 FMULD Inherent | | # 18F7 FDIVD Inherent | | # 18F8 FSQRTD Inherent | | # 18F9 FSNGJD Inherent | | # 18FA FCMPD Inherent | | # 18FB FMAXD Inherent | | # 18FC FCLASSD Inherent | -------------------------------------- &lt;/code&gt;&lt;/pre&gt;&lt;/div&gt;&lt;/div&gt;
		
		</content:encoded>


		

	</item>
<item xml:lang="en">
		<title>Internal registers</title>
		<link>https://63f09.systella.fr/cpu-63f09/article/internal-registers</link>
		<guid isPermaLink="true">https://63f09.systella.fr/cpu-63f09/article/internal-registers</guid>
		<dc:date>2024-05-28T12:24:57Z</dc:date>
		<dc:format>text/html</dc:format>
		<dc:language>en</dc:language>
		<dc:creator>63F09</dc:creator>



		<description>
&lt;p&gt;&lt;span class=&#034;caps&#034;&gt;MD&lt;/span&gt; register is always accessible as it changes the processor's operating mode. Due to internal data path, 0 or Z (zero) register is available for transfer and exchange instructions. 6809 mode Registers 8 bits 8 bits A B Virtual D (16 bits) Z &lt;span class=&#034;caps&#034;&gt;DP&lt;/span&gt; &lt;span class=&#034;caps&#034;&gt;CC&lt;/span&gt; &lt;span class=&#034;caps&#034;&gt;MD&lt;/span&gt; 16 bits X Y U S &lt;span class=&#034;caps&#034;&gt;PC&lt;/span&gt; &lt;br class='autobr' /&gt; &lt;span class=&#034;caps&#034;&gt;MD&lt;/span&gt; bits &lt;span class=&#034;caps&#034;&gt;MD&lt;/span&gt; &lt;span class=&#034;caps&#034;&gt;DZ&lt;/span&gt; &lt;span class=&#034;caps&#034;&gt;IL&lt;/span&gt; &lt;span class=&#034;caps&#034;&gt;FPU&lt;/span&gt; 32 &lt;span class=&#034;caps&#034;&gt;IS&lt;/span&gt; &lt;span class=&#034;caps&#034;&gt;ED&lt;/span&gt; &lt;span class=&#034;caps&#034;&gt;FM&lt;/span&gt; &lt;span class=&#034;caps&#034;&gt;EM&lt;/span&gt; &lt;span class=&#034;caps&#034;&gt;EM&lt;/span&gt;: 0: 6809 mode 1: 6309 mode &lt;span class=&#034;caps&#034;&gt;FM&lt;/span&gt;: 0: &lt;span class=&#034;caps&#034;&gt;FIRQ&lt;/span&gt; treated as fast interrupt request 1: &lt;span class=&#034;caps&#034;&gt;FIRQ&lt;/span&gt; treated as interrupt request &lt;span class=&#034;caps&#034;&gt;ED&lt;/span&gt;: 0: &lt;span class=&#034;caps&#034;&gt;EIRQ&lt;/span&gt; [1] active on level 1:&#160;(&#8230;)&lt;/p&gt;


-
&lt;a href="https://63f09.systella.fr/cpu-63f09/" rel="directory"&gt;CPU 63F09&lt;/a&gt;


		</description>


 <content:encoded>&lt;div class='rss_texte'&gt;&lt;p&gt;&lt;span class=&#034;caps&#034;&gt;MD&lt;/span&gt; register is always accessible as it changes the processor's operating mode. Due to internal data path, 0 or Z (zero) register is available for transfer and exchange instructions.&lt;/p&gt;
&lt;h2 class=&#034;spip&#034;&gt;6809 mode&lt;/h2&gt;&lt;table class=&#034;table spip&#034;&gt;
&lt;caption&gt;Registers&lt;/caption&gt;
&lt;thead&gt;&lt;tr class='row_first'&gt;&lt;th id='idd40d_c0'&gt; 8 bits &lt;/th&gt;&lt;th id='idd40d_c1'&gt; 8 bits &lt;/th&gt;&lt;/tr&gt;&lt;/thead&gt;
&lt;tbody&gt;
&lt;tr class='row_odd odd'&gt;
&lt;td headers='idd40d_c0'&gt;A&lt;/td&gt;
&lt;td headers='idd40d_c1'&gt;B&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_even even'&gt;
&lt;td colspan='2' headers='idd40d_c0'&gt;Virtual D (16 bits)&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_odd odd'&gt;
&lt;td colspan='2' headers='idd40d_c0'&gt;Z&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_even even'&gt;
&lt;td headers='idd40d_c0'&gt;&lt;span class=&#034;caps&#034;&gt;DP&lt;/span&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_odd odd'&gt;
&lt;td headers='idd40d_c0'&gt;&lt;span class=&#034;caps&#034;&gt;CC&lt;/span&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_even even'&gt;
&lt;td headers='idd40d_c0'&gt;&lt;span class=&#034;caps&#034;&gt;MD&lt;/span&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;/tbody&gt;
&lt;/table&gt;&lt;table class=&#034;table spip&#034;&gt;
&lt;thead&gt;&lt;tr class='row_first'&gt;&lt;th id='idef94_c0'&gt; 16 bits &lt;/th&gt;&lt;/tr&gt;&lt;/thead&gt;
&lt;tbody&gt;
&lt;tr class='row_odd odd'&gt;
&lt;td headers='idef94_c0'&gt;X&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_even even'&gt;
&lt;td headers='idef94_c0'&gt;Y&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_odd odd'&gt;
&lt;td headers='idef94_c0'&gt;U&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_even even'&gt;
&lt;td headers='idef94_c0'&gt;S&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_odd odd'&gt;
&lt;td headers='idef94_c0'&gt;&lt;span class=&#034;caps&#034;&gt;PC&lt;/span&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;/tbody&gt;
&lt;/table&gt;
&lt;p&gt;&lt;strong&gt; &lt;span class=&#034;caps&#034;&gt;MD&lt;/span&gt; bits &lt;/strong&gt;&lt;/p&gt;
&lt;table class=&#034;table spip&#034;&gt;
&lt;caption&gt;&lt;span class=&#034;caps&#034;&gt;MD&lt;/span&gt;&lt;/caption&gt;
&lt;tbody&gt;
&lt;tr class='row_odd odd'&gt;
&lt;td&gt;&lt;span class=&#034;caps&#034;&gt;DZ&lt;/span&gt;&lt;/td&gt;
&lt;td&gt;&lt;span class=&#034;caps&#034;&gt;IL&lt;/span&gt;&lt;/td&gt;
&lt;td&gt;&lt;span class=&#034;caps&#034;&gt;FPU&lt;/span&gt;&lt;/td&gt;
&lt;td class='numeric '&gt;32&lt;/td&gt;
&lt;td&gt;&lt;span class=&#034;caps&#034;&gt;IS&lt;/span&gt;&lt;/td&gt;
&lt;td&gt;&lt;span class=&#034;caps&#034;&gt;ED&lt;/span&gt;&lt;/td&gt;
&lt;td&gt;&lt;span class=&#034;caps&#034;&gt;FM&lt;/span&gt;&lt;/td&gt;
&lt;td&gt;&lt;span class=&#034;caps&#034;&gt;EM&lt;/span&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;/tbody&gt;
&lt;/table&gt;&lt;ul class=&#034;spip&#034; role=&#034;list&#034;&gt;&lt;li&gt; &lt;span class=&#034;caps&#034;&gt;EM&lt;/span&gt;:
&lt;ul class=&#034;spip&#034; role=&#034;list&#034;&gt;&lt;li&gt; 0: 6809 mode&lt;/li&gt;&lt;li&gt; 1: 6309 mode&lt;/li&gt;&lt;/ul&gt;&lt;/li&gt;&lt;li&gt; &lt;span class=&#034;caps&#034;&gt;FM&lt;/span&gt;:
&lt;ul class=&#034;spip&#034; role=&#034;list&#034;&gt;&lt;li&gt; 0: &lt;span class=&#034;caps&#034;&gt;FIRQ&lt;/span&gt; treated as fast interrupt request&lt;/li&gt;&lt;li&gt; 1: &lt;span class=&#034;caps&#034;&gt;FIRQ&lt;/span&gt; treated as interrupt request&lt;/li&gt;&lt;/ul&gt;&lt;/li&gt;&lt;li&gt; &lt;span class=&#034;caps&#034;&gt;ED&lt;/span&gt;:
&lt;ul class=&#034;spip&#034; role=&#034;list&#034;&gt;&lt;li&gt; 0: &lt;span class=&#034;caps&#034;&gt;EIRQ&lt;/span&gt;&lt;span class=&#034;spip_note_ref&#034;&gt; [&lt;a href=&#034;#nb2-1&#034; class=&#034;spip_note&#034; rel=&#034;appendix&#034; title=&#034;EIRQ (extended interrupt request): 24 new hardware interrupt requests (&#8230;)&#034; id=&#034;nh2-1&#034;&gt;1&lt;/a&gt;]&lt;/span&gt; active on level&lt;/li&gt;&lt;li&gt; 1: &lt;span class=&#034;caps&#034;&gt;EIRQ&lt;/span&gt; active on edge&lt;/li&gt;&lt;/ul&gt;&lt;/li&gt;&lt;li&gt; &lt;span class=&#034;caps&#034;&gt;IS&lt;/span&gt; :
&lt;ul class=&#034;spip&#034; role=&#034;list&#034;&gt;&lt;li&gt; 0: interrupt requests are not disabled after an interrupt routine is called.&lt;/li&gt;&lt;li&gt; 1: interrupt requests are disabled after an interrupt routine is called until S stack pointer is loaded with a new value. Used to change &lt;span class=&#034;caps&#034;&gt;CPU&lt;/span&gt; context with &lt;span class=&#034;caps&#034;&gt;MMU&lt;/span&gt;.&lt;/li&gt;&lt;/ul&gt;&lt;/li&gt;&lt;li&gt; 32 : ignored if &lt;span class=&#034;caps&#034;&gt;EM&lt;/span&gt; is set to 0.
&lt;ul class=&#034;spip&#034; role=&#034;list&#034;&gt;&lt;li&gt; 0 : 6309 mode (16 bits)&lt;/li&gt;&lt;li&gt; 1 : 63F09 mode (32 bits)&lt;/li&gt;&lt;/ul&gt;&lt;/li&gt;&lt;li&gt; &lt;span class=&#034;caps&#034;&gt;FPU&lt;/span&gt; : ignored if &lt;span class=&#034;caps&#034;&gt;EM&lt;/span&gt; is set to 0.
&lt;ul class=&#034;spip&#034; role=&#034;list&#034;&gt;&lt;li&gt; 0 : no &lt;span class=&#034;caps&#034;&gt;FPU&lt;/span&gt;&lt;/li&gt;&lt;li&gt; 1 : &lt;span class=&#034;caps&#034;&gt;IEEE&lt;/span&gt; &lt;span class=&#034;caps&#034;&gt;FPU&lt;/span&gt;&lt;/li&gt;&lt;/ul&gt;&lt;/li&gt;&lt;li&gt; &lt;span class=&#034;caps&#034;&gt;IL&lt;/span&gt; : output flag, illegal instruction&lt;/li&gt;&lt;li&gt; &lt;span class=&#034;caps&#034;&gt;DZ&lt;/span&gt; : output flag, division by zero&lt;/li&gt;&lt;/ul&gt;&lt;h2 class=&#034;spip&#034;&gt;6309 mode&lt;/h2&gt;&lt;table class=&#034;table spip&#034;&gt;
&lt;caption&gt;Registers&lt;/caption&gt;
&lt;thead&gt;&lt;tr class='row_first'&gt;&lt;th id='id3666_c0'&gt; 8 bits &lt;/th&gt;&lt;th id='id3666_c1'&gt; 8 bits &lt;/th&gt;&lt;th id='id3666_c2'&gt; 8 bits &lt;/th&gt;&lt;th id='id3666_c3'&gt; 8 bits &lt;/th&gt;&lt;/tr&gt;&lt;/thead&gt;
&lt;tbody&gt;
&lt;tr class='row_odd odd'&gt;
&lt;td headers='id3666_c0'&gt;A&lt;/td&gt;
&lt;td headers='id3666_c1'&gt;B&lt;/td&gt;
&lt;td headers='id3666_c2'&gt;E&lt;/td&gt;
&lt;td headers='id3666_c3'&gt;F&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_even even'&gt;
&lt;td colspan='2' headers='id3666_c0'&gt;Virtual D (16 bits)&lt;/td&gt;
&lt;td colspan='2' headers='id3666_c2'&gt;Virtual W (16 bits)&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_odd odd'&gt;
&lt;td colspan='4' headers='id3666_c0'&gt;Virtual Q (32 bits)&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_even even'&gt;
&lt;td colspan='2' headers='id3666_c0'&gt;Z&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_odd odd'&gt;
&lt;td headers='id3666_c0'&gt;&lt;span class=&#034;caps&#034;&gt;DP&lt;/span&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_even even'&gt;
&lt;td headers='id3666_c0'&gt;&lt;span class=&#034;caps&#034;&gt;CC&lt;/span&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_odd odd'&gt;
&lt;td headers='id3666_c0'&gt;&lt;span class=&#034;caps&#034;&gt;MD&lt;/span&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;/tbody&gt;
&lt;/table&gt;&lt;table class=&#034;table spip&#034;&gt;
&lt;thead&gt;&lt;tr class='row_first'&gt;&lt;th id='id66ca_c0'&gt; 16 bits &lt;/th&gt;&lt;/tr&gt;&lt;/thead&gt;
&lt;tbody&gt;
&lt;tr class='row_odd odd'&gt;
&lt;td headers='id66ca_c0'&gt;X&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_even even'&gt;
&lt;td headers='id66ca_c0'&gt;Y&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_odd odd'&gt;
&lt;td headers='id66ca_c0'&gt;U&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_even even'&gt;
&lt;td headers='id66ca_c0'&gt;S&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_odd odd'&gt;
&lt;td headers='id66ca_c0'&gt;V&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_even even'&gt;
&lt;td headers='id66ca_c0'&gt;&lt;span class=&#034;caps&#034;&gt;PC&lt;/span&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;/tbody&gt;
&lt;/table&gt;&lt;h2 class=&#034;spip&#034;&gt;63F09 mode&lt;/h2&gt;
&lt;p&gt;Note that 63F09 in full 63F09 mode does not contain 0 or Z (zero) register. 63F09 is a 32 bits extension of regular 6309.&lt;/p&gt;
&lt;table class=&#034;table spip&#034;&gt;
&lt;caption&gt;Registers&lt;/caption&gt;
&lt;thead&gt;&lt;tr class='row_first'&gt;&lt;th id='id4e9c_c0'&gt; 8 bits &lt;/th&gt;&lt;th id='id4e9c_c1'&gt; 8 bits &lt;/th&gt;&lt;th id='id4e9c_c2'&gt; 8 bits &lt;/th&gt;&lt;th id='id4e9c_c3'&gt; 8 bits &lt;/th&gt;&lt;th id='id4e9c_c4'&gt; 32 bits &lt;/th&gt;&lt;/tr&gt;&lt;/thead&gt;
&lt;tbody&gt;
&lt;tr class='row_odd odd'&gt;
&lt;td headers='id4e9c_c0'&gt;A&lt;/td&gt;
&lt;td headers='id4e9c_c1'&gt;B&lt;/td&gt;
&lt;td headers='id4e9c_c2'&gt;E&lt;/td&gt;
&lt;td headers='id4e9c_c3'&gt;F&lt;/td&gt;
&lt;td rowspan='3' headers='id4e9c_c4'&gt;V&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_even even'&gt;
&lt;td colspan='2' headers='id4e9c_c0'&gt;Virtual D (16 bits)&lt;/td&gt;
&lt;td colspan='2' headers='id4e9c_c2'&gt;Virtual W (16 bits)&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_odd odd'&gt;
&lt;td colspan='4' headers='id4e9c_c0'&gt;Virtual Q (32 bits)&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_even even'&gt;
&lt;td colspan='5' headers='id4e9c_c0'&gt;Virtual O (64 bits)&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_odd odd'&gt;
&lt;td colspan='4' headers='id4e9c_c0'&gt;&lt;span class=&#034;caps&#034;&gt;MD&lt;/span&gt; (32 bits)&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_even even'&gt;
&lt;td colspan='2' headers='id4e9c_c0'&gt;&lt;span class=&#034;caps&#034;&gt;DS&lt;/span&gt; (16 bits)&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_odd odd'&gt;
&lt;td headers='id4e9c_c0'&gt;&lt;span class=&#034;caps&#034;&gt;DP&lt;/span&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_even even'&gt;
&lt;td headers='id4e9c_c0'&gt;&lt;span class=&#034;caps&#034;&gt;CC&lt;/span&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;/tbody&gt;
&lt;/table&gt;&lt;table class=&#034;table spip&#034;&gt;
&lt;thead&gt;&lt;tr class='row_first'&gt;&lt;th id='id7f0f_c0'&gt; 32 bits &lt;/th&gt;&lt;/tr&gt;&lt;/thead&gt;
&lt;tbody&gt;
&lt;tr class='row_odd odd'&gt;
&lt;td headers='id7f0f_c0'&gt;X&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_even even'&gt;
&lt;td headers='id7f0f_c0'&gt;Y&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_odd odd'&gt;
&lt;td headers='id7f0f_c0'&gt;U&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_even even'&gt;
&lt;td headers='id7f0f_c0'&gt;S&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_odd odd'&gt;
&lt;td headers='id7f0f_c0'&gt;&lt;span class=&#034;caps&#034;&gt;PC&lt;/span&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;/tbody&gt;
&lt;/table&gt;&lt;h2 class=&#034;spip&#034;&gt;63F09 mode with &lt;span class=&#034;caps&#034;&gt;FPU&lt;/span&gt;&lt;/h2&gt;&lt;table class=&#034;table spip&#034;&gt;
&lt;caption&gt;Registers&lt;/caption&gt;
&lt;thead&gt;&lt;tr class='row_first'&gt;&lt;th id='id4e9c_c0'&gt; 8 bits &lt;/th&gt;&lt;th id='id4e9c_c1'&gt; 8 bits &lt;/th&gt;&lt;th id='id4e9c_c2'&gt; 8 bits &lt;/th&gt;&lt;th id='id4e9c_c3'&gt; 8 bits &lt;/th&gt;&lt;th id='id4e9c_c4'&gt; 32 bits &lt;/th&gt;&lt;/tr&gt;&lt;/thead&gt;
&lt;tbody&gt;
&lt;tr class='row_odd odd'&gt;
&lt;td headers='id4e9c_c0'&gt;A&lt;/td&gt;
&lt;td headers='id4e9c_c1'&gt;B&lt;/td&gt;
&lt;td headers='id4e9c_c2'&gt;E&lt;/td&gt;
&lt;td headers='id4e9c_c3'&gt;F&lt;/td&gt;
&lt;td rowspan='3' headers='id4e9c_c4'&gt;V&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_even even'&gt;
&lt;td colspan='2' headers='id4e9c_c0'&gt;Virtual D (16 bits)&lt;/td&gt;
&lt;td colspan='2' headers='id4e9c_c2'&gt;Virtual W (16 bits)&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_odd odd'&gt;
&lt;td colspan='4' headers='id4e9c_c0'&gt;Virtual Q (32 bits)&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_even even'&gt;
&lt;td colspan='5' headers='id4e9c_c0'&gt;Virtual O (64 bits)&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_odd odd'&gt;
&lt;td colspan='4' headers='id4e9c_c0'&gt;&lt;span class=&#034;caps&#034;&gt;MD&lt;/span&gt; (32 bits)&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_even even'&gt;
&lt;td colspan='2' headers='id4e9c_c0'&gt;&lt;span class=&#034;caps&#034;&gt;DS&lt;/span&gt; (16 bits)&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_odd odd'&gt;
&lt;td headers='id4e9c_c0'&gt;&lt;span class=&#034;caps&#034;&gt;DP&lt;/span&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_even even'&gt;
&lt;td headers='id4e9c_c0'&gt;&lt;span class=&#034;caps&#034;&gt;CC&lt;/span&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;/tbody&gt;
&lt;/table&gt;&lt;table class=&#034;table spip&#034;&gt;
&lt;thead&gt;&lt;tr class='row_first'&gt;&lt;th id='id7f0f_c0'&gt; 32 bits &lt;/th&gt;&lt;/tr&gt;&lt;/thead&gt;
&lt;tbody&gt;
&lt;tr class='row_odd odd'&gt;
&lt;td headers='id7f0f_c0'&gt;X&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_even even'&gt;
&lt;td headers='id7f0f_c0'&gt;Y&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_odd odd'&gt;
&lt;td headers='id7f0f_c0'&gt;U&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_even even'&gt;
&lt;td headers='id7f0f_c0'&gt;S&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_odd odd'&gt;
&lt;td headers='id7f0f_c0'&gt;&lt;span class=&#034;caps&#034;&gt;PC&lt;/span&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;/tbody&gt;
&lt;/table&gt;
&lt;p&gt;Please note that &lt;span class=&#034;caps&#034;&gt;MD&lt;/span&gt; register is in 63F09 mode a 32 bits register. Eight &lt;span class=&#034;caps&#034;&gt;LSB&lt;/span&gt; bits act as 6309 standard &lt;span class=&#034;caps&#034;&gt;MD&lt;/span&gt; register. Other bits are used as &lt;span class=&#034;caps&#034;&gt;EIRQ&lt;/span&gt; masks.&lt;/p&gt;
&lt;table class=&#034;table spip&#034;&gt;
&lt;tbody&gt;
&lt;tr class='row_odd odd'&gt;
&lt;td&gt;&lt;strong&gt; 64 bits &lt;/strong&gt; (single and double precision floating point registers)&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_even even'&gt;
&lt;td&gt;&lt;span class=&#034;caps&#034;&gt;FP1&lt;/span&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_odd odd'&gt;
&lt;td&gt;&lt;span class=&#034;caps&#034;&gt;FP2&lt;/span&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_even even'&gt;
&lt;td&gt;&lt;span class=&#034;caps&#034;&gt;FP3&lt;/span&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_odd odd'&gt;
&lt;td&gt;&lt;span class=&#034;caps&#034;&gt;FP4&lt;/span&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_even even'&gt;
&lt;td&gt;&lt;span class=&#034;caps&#034;&gt;FP5&lt;/span&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_odd odd'&gt;
&lt;td&gt;&lt;span class=&#034;caps&#034;&gt;FP6&lt;/span&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_even even'&gt;
&lt;td&gt;&lt;span class=&#034;caps&#034;&gt;FP7&lt;/span&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_odd odd'&gt;
&lt;td&gt;&lt;span class=&#034;caps&#034;&gt;FP8&lt;/span&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_even even'&gt;
&lt;td&gt;&lt;span class=&#034;caps&#034;&gt;FP9&lt;/span&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_odd odd'&gt;
&lt;td&gt;&lt;span class=&#034;caps&#034;&gt;FP10&lt;/span&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_even even'&gt;
&lt;td&gt;&lt;span class=&#034;caps&#034;&gt;FP11&lt;/span&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_odd odd'&gt;
&lt;td&gt;&lt;span class=&#034;caps&#034;&gt;FP12&lt;/span&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_even even'&gt;
&lt;td&gt;&lt;span class=&#034;caps&#034;&gt;FP13&lt;/span&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_odd odd'&gt;
&lt;td&gt;&lt;span class=&#034;caps&#034;&gt;FP14&lt;/span&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_even even'&gt;
&lt;td&gt;&lt;span class=&#034;caps&#034;&gt;FP15&lt;/span&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;tr class='row_odd odd'&gt;
&lt;td&gt;&lt;span class=&#034;caps&#034;&gt;FP16&lt;/span&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;/tbody&gt;
&lt;/table&gt;&lt;table class=&#034;table spip&#034;&gt;
&lt;thead&gt;&lt;tr class='row_first'&gt;&lt;th id='id39cf_c0'&gt; 8 bits &lt;/th&gt;&lt;/tr&gt;&lt;/thead&gt;
&lt;tbody&gt;
&lt;tr class='row_odd odd'&gt;
&lt;td headers='id39cf_c0'&gt;&lt;span class=&#034;caps&#034;&gt;FPUCC&lt;/span&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;/tbody&gt;
&lt;/table&gt;
&lt;p&gt;&lt;strong&gt;&lt;span class=&#034;caps&#034;&gt;FPUCC&lt;/span&gt;&lt;/strong&gt;&lt;br class='autobr' /&gt;
&lt;span class=&#034;caps&#034;&gt;FPUCC&lt;/span&gt; contains three bits for rounding mode and five bits for status. It cannot be direcly addressed.&lt;/p&gt;
&lt;table class=&#034;table spip&#034;&gt;
&lt;caption&gt;&lt;span class=&#034;caps&#034;&gt;FPUCC&lt;/span&gt;&lt;/caption&gt;
&lt;tbody&gt;
&lt;tr class='row_odd odd'&gt;
&lt;td&gt;&lt;span class=&#034;caps&#034;&gt;RND2&lt;/span&gt;&lt;/td&gt;
&lt;td&gt;&lt;span class=&#034;caps&#034;&gt;RND1&lt;/span&gt;&lt;/td&gt;
&lt;td&gt;&lt;span class=&#034;caps&#034;&gt;RND0&lt;/span&gt;&lt;/td&gt;
&lt;td&gt;&lt;span class=&#034;caps&#034;&gt;NV&lt;/span&gt;&lt;/td&gt;
&lt;td&gt;&lt;span class=&#034;caps&#034;&gt;DZ&lt;/span&gt;&lt;/td&gt;
&lt;td&gt;&lt;span class=&#034;caps&#034;&gt;OF&lt;/span&gt;&lt;/td&gt;
&lt;td&gt;&lt;span class=&#034;caps&#034;&gt;UF&lt;/span&gt;&lt;/td&gt;
&lt;td&gt;&lt;span class=&#034;caps&#034;&gt;NX&lt;/span&gt;&lt;/td&gt;&lt;/tr&gt;
&lt;/tbody&gt;
&lt;/table&gt;&lt;ul class=&#034;spip&#034; role=&#034;list&#034;&gt;&lt;li&gt; &lt;span class=&#034;caps&#034;&gt;RND2&lt;/span&gt;, &lt;span class=&#034;caps&#034;&gt;RND1&lt;/span&gt;, &lt;span class=&#034;caps&#034;&gt;RND0&lt;/span&gt; are set by &lt;span class=&#034;caps&#034;&gt;SETRNE&lt;/span&gt;, &lt;span class=&#034;caps&#034;&gt;SETRTZ&lt;/span&gt;, &lt;span class=&#034;caps&#034;&gt;SETRDN&lt;/span&gt;, &lt;span class=&#034;caps&#034;&gt;SETRUP&lt;/span&gt;, &lt;span class=&#034;caps&#034;&gt;SETRMM&lt;/span&gt; or &lt;span class=&#034;caps&#034;&gt;SETDYN&lt;/span&gt; instruction.&lt;/li&gt;&lt;li&gt; other bits are used as flags set by &lt;span class=&#034;caps&#034;&gt;FPU&lt;/span&gt;:
&lt;ul class=&#034;spip&#034; role=&#034;list&#034;&gt;&lt;li&gt; &lt;span class=&#034;caps&#034;&gt;NV&lt;/span&gt; : invalid result&lt;/li&gt;&lt;li&gt; &lt;span class=&#034;caps&#034;&gt;DZ&lt;/span&gt; : division by zero&lt;/li&gt;&lt;li&gt; &lt;span class=&#034;caps&#034;&gt;OF&lt;/span&gt; : overflow&lt;/li&gt;&lt;li&gt; &lt;span class=&#034;caps&#034;&gt;UF&lt;/span&gt; : underflow&lt;/li&gt;&lt;li&gt; &lt;span class=&#034;caps&#034;&gt;NX&lt;/span&gt; : inexact&lt;/li&gt;&lt;/ul&gt;&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;These flags can be tested by (L)&lt;span class=&#034;caps&#034;&gt;BNV&lt;/span&gt;, (L)&lt;span class=&#034;caps&#034;&gt;BDZ&lt;/span&gt;, (L)&lt;span class=&#034;caps&#034;&gt;BOV&lt;/span&gt;, (L)&lt;span class=&#034;caps&#034;&gt;BUN&lt;/span&gt; and (L)&lt;span class=&#034;caps&#034;&gt;BIX&lt;/span&gt; instructions. Two other branch instructions (L)&lt;span class=&#034;caps&#034;&gt;BFT&lt;/span&gt; and (L)&lt;span class=&#034;caps&#034;&gt;BFF&lt;/span&gt; are used to test boolean result of &lt;span class=&#034;caps&#034;&gt;FPU&lt;/span&gt; operation (for example &lt;span class=&#034;caps&#034;&gt;FCMPS&lt;/span&gt;).&lt;/p&gt;&lt;/div&gt;
		&lt;hr /&gt;
		&lt;div class='rss_notes'&gt;&lt;div id=&#034;nb2-1&#034;&gt;
&lt;p&gt;&lt;span class=&#034;spip_note_ref&#034;&gt;[&lt;a href=&#034;#nh2-1&#034; class=&#034;spip_note&#034; title=&#034;Footnotes 2-1&#034; rev=&#034;appendix&#034;&gt;1&lt;/a&gt;] &lt;/span&gt;&lt;span class=&#034;caps&#034;&gt;&lt;span class=&#034;caps&#034;&gt;EIRQ&lt;/span&gt;&lt;/span&gt; (extended interrupt request): 24 new hardware interrupt requests available in 63F09 mode.&lt;/p&gt;
&lt;/div&gt;&lt;/div&gt;
		
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	</item>
<item xml:lang="en">
		<title>FPU</title>
		<link>https://63f09.systella.fr/cpu-63f09/article/fpu</link>
		<guid isPermaLink="true">https://63f09.systella.fr/cpu-63f09/article/fpu</guid>
		<dc:date>2024-05-28T12:24:09Z</dc:date>
		<dc:format>text/html</dc:format>
		<dc:language>en</dc:language>
		<dc:creator>63F09</dc:creator>



		<description>

-
&lt;a href="https://63f09.systella.fr/cpu-63f09/" rel="directory"&gt;CPU 63F09&lt;/a&gt;


		</description>


 <content:encoded>
		</content:encoded>


		

	</item>
<item xml:lang="en">
		<title>A 8/64 bits CPU</title>
		<link>https://63f09.systella.fr/cpu-63f09/article/a-8-64-bits-cpu</link>
		<guid isPermaLink="true">https://63f09.systella.fr/cpu-63f09/article/a-8-64-bits-cpu</guid>
		<dc:date>2024-05-28T12:08:18Z</dc:date>
		<dc:format>text/html</dc:format>
		<dc:language>en</dc:language>
		<dc:creator>63F09</dc:creator>



		<description>
&lt;p&gt;63F09 is a modern &lt;span class=&#034;caps&#034;&gt;CPU&lt;/span&gt; full compatible with old &lt;span class=&#034;caps&#034;&gt;MC6809&lt;/span&gt;. It presents only one difference with &lt;span class=&#034;caps&#034;&gt;HD6309&lt;/span&gt;, it don't have a 0 register. &lt;br class='autobr' /&gt;
If the first instruction after reset is &lt;span class=&#034;caps&#034;&gt;LDMD&lt;/span&gt;, &lt;span class=&#034;caps&#034;&gt;CPU&lt;/span&gt; can enter in 6309 mode (16 bits) or 63F09 mode (32 bits) with or without &lt;span class=&#034;caps&#034;&gt;FPU&lt;/span&gt;. &lt;br class='autobr' /&gt;
In 63F09 mode, there are a lot of new instructions. For example: hardwired multiplications and division (until 64 bits); 32 and 64 bits arithmetic; &lt;span class=&#034;caps&#034;&gt;FPU&lt;/span&gt; that handle simple and double precision floats; 32 bits addresses (36 bits with&#160;(&#8230;)&lt;/p&gt;


-
&lt;a href="https://63f09.systella.fr/cpu-63f09/" rel="directory"&gt;CPU 63F09&lt;/a&gt;


		</description>


 <content:encoded>&lt;div class='rss_texte'&gt;&lt;p&gt;63F09 is a modern &lt;span class=&#034;caps&#034;&gt;CPU&lt;/span&gt; full compatible with old &lt;span class=&#034;caps&#034;&gt;MC6809&lt;/span&gt;. It presents only one difference with &lt;span class=&#034;caps&#034;&gt;HD6309&lt;/span&gt;, it don't have a 0 register.&lt;/p&gt;
&lt;p&gt;If the first instruction after reset is &lt;span class=&#034;caps&#034;&gt;LDMD&lt;/span&gt;, &lt;span class=&#034;caps&#034;&gt;CPU&lt;/span&gt; can enter in 6309 mode (16 bits) or 63F09 mode (32 bits) with or without &lt;span class=&#034;caps&#034;&gt;FPU&lt;/span&gt;.&lt;/p&gt;
&lt;p&gt;In 63F09 mode, there are a lot of new instructions. For example:&lt;/p&gt;
&lt;ul class=&#034;spip&#034; role=&#034;list&#034;&gt;&lt;li&gt; hardwired multiplications and division (until 64 bits);&lt;/li&gt;&lt;li&gt; 32 and 64 bits arithmetic;&lt;/li&gt;&lt;li&gt; &lt;span class=&#034;caps&#034;&gt;FPU&lt;/span&gt; that handle simple and double precision floats;&lt;/li&gt;&lt;li&gt; 32 bits addresses (36 bits with &lt;span class=&#034;caps&#034;&gt;MMU&lt;/span&gt;)...&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;Twenty-seven interrupt requests are available:&lt;/p&gt;
&lt;ul class=&#034;spip&#034; role=&#034;list&#034;&gt;&lt;li&gt; &lt;span class=&#034;caps&#034;&gt;NMI&lt;/span&gt;&lt;/li&gt;&lt;li&gt; &lt;span class=&#034;caps&#034;&gt;IRQ&lt;/span&gt;&lt;/li&gt;&lt;li&gt; &lt;span class=&#034;caps&#034;&gt;FIRQ&lt;/span&gt;&lt;/li&gt;&lt;li&gt; twenty-four &lt;span class=&#034;caps&#034;&gt;EIRQ&lt;/span&gt; (extended interrupt requests) active on edge or level. These interrupt requests can be configured to act as a regular or fast interrupt.&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;63F09 clock is given by an external &lt;span class=&#034;caps&#034;&gt;TTL&lt;/span&gt; clock running at 24 MHz. This clock cannot be modified without reconfiguration of internal &lt;span class=&#034;caps&#034;&gt;PLL&lt;/span&gt;.&lt;/p&gt;
&lt;div class='spip_document_4 spip_document spip_documents spip_document_image spip_documents_center spip_document_center'&gt;
&lt;figure class=&#034;spip_doc_inner&#034;&gt; &lt;a href='https://63f09.systella.fr/IMG/jpg/cpu.jpg' class=&#034;spip_doc_lien mediabox&#034; type=&#034;image/jpeg&#034;&gt; &lt;img src='https://63f09.systella.fr/IMG/jpg/cpu.jpg?1717244693' width='500' height='145' alt='' /&gt;&lt;/a&gt;
&lt;/figure&gt;
&lt;/div&gt;&lt;/div&gt;
		
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