63F09

The 63F09: a 6809-derived 8/64-bit CPU

63F09 — 2026-09-23T12:24:28Z

The 63F09 is a custom processor, designed from scratch in VHDL by its author (running on real FPGA hardware), that extends the classic Motorola 6809 8-bit CPU into a three-level family: the base 6809 instruction set, a superset compatible with the Hitachi HD6309 (“6309 native mode”), and the 63F09 itself, which adds a 32-bit addressing/register mode and an optional hardware floating-point unit (63F09HF). Unlike the original 6809, which was strictly an 8/16-bit microcontroller-class chip, the 63F09 in its 32-bit mode addresses up to 64 GB of memory — the design target is a real, general-purpose CPU, not a microcontroller.

Register file

The 63F09 keeps the 6809's original registers (PC, S, U, X, Y, DP, CC, A, B) and layers new ones on top as each mode is unlocked:

– E, F, V become available from 6309-native mode onward;
– DS, a second direct-page selector, is 63F09-only;
– composite pseudo-registers combine the raw ones: D = A:B (always available), W = E:F (6309+), Q = D:W (6309+, always 32 bits — available in both 16-bit and 32-bit CPU modes, unlike X/Y/U/S/V which only widen to 32 bits in 63F09 32-bit mode), and O = Q:V, a 64-bit “octo” register available in 63F09 32-bit mode only.

A notable ABI property: on this port's calling convention, every general-purpose register is caller-saved. There is no callee-saved register set to spill in a prologue, which simplifies function entry/exit code generation considerably.

Direct-page addressing

Like the original 6809, the 63F09 keeps a fast “direct page” addressing mode selected by the DP register (and, in 32-bit mode, an additional DS register selecting a 16 MB window). A GCC backend pass on this port automatically detects small static/global variables accessed repeatedly inside a loop, forces them into a 256-byte-aligned page, and rewrites in-loop accesses to use this one-byte-shorter, faster addressing form — entirely automatically, with no source-level annotation required.

Hardware floating point

The optional 63F09HF variant adds a real hardware FPU: a 16-deep stack of FP0-FP15 registers (single and double precision), fused multiply-add, square root, and the usual arithmetic/comparison/conversion set. Comparisons report their result through the CPU's own condition-code register rather than the FP stack, which turned out to be exactly the contract GCC's stack-register allocator (originally written for the x87) expects.

Toolchain and software support

The 63F09 is backed by a genuinely working, from-scratch GNU toolchain port: binutils (assembler, linker, disassembler), GDB, and a GCC backend supporting C and Fortran, all built up and verified against real compiled and linked output rather than assumed correct. A newlib C library port covers four distinct hosting environments — bare metal, two vintage 6809 operating systems (FLEX9 and UniFLEX), and a simulated development SoC with a real UART console — selected at link time via dedicated crt0 startup files and linker emulations.

Advantages

– A simple, well-understood 8-bit instruction set as its foundation, extended rather than replaced — 6809 and 6309 object code and assembly-level habits remain directly relevant.
– Genuine 32-bit addressing and a real hardware FPU bolted onto that familiar base, without abandoning its register model or addressing-mode philosophy.
– Automatic direct-page optimization gives small, loop-hot data a real, compiler-managed speed win with zero source changes.
– An entirely caller-saved register convention keeps function prologues/epilogues trivially cheap.
– A complete, real GCC/binutils/newlib toolchain exists today: C and Fortran programs can actually be compiled, assembled, linked, and (statically) inspected, not just theorized about.
– Being an open, from-scratch VHDL design that runs on FPGA, the whole system — CPU, ISA, and toolchain — is fully inspectable and modifiable, which has made it practical to find and fix real bugs by cross-checking compiler output against the hardware description directly.

Limitations and open issues

– Some hardware-backed arithmetic (64x64 multiply, 8x8 multiply) is not yet exposed as GCC instruction patterns, so the compiler still emits slower software fallbacks for cases the CPU could handle directly.
– libgfortran, GCC's Fortran runtime, is too large to fit in the 64 KB address space of the 16-bit submodes once anything beyond trivial I/O is linked in — full-featured Fortran I/O is presently a 32-bit-mode-only proposition.

In short

The 63F09 is best understood as “what if the 6809 had kept growing” rather than a clean-sheet modern design: it trades the novelty of a from-scratch ISA for the comfort of a genuinely simple, fully understood 8-bit ancestor, extended just enough — 32-bit addressing, a real FPU, automatic direct-page optimization — to make real systems.

Opcodes

63F09 — 2024-05-28T12:25:30Z

Warning: in 63F09 mode (32 bits), there is no 0 or Z (zero) register. Nevertheless, in 6309 mode (16 bits), Z is usable with EXG and TFR opcodes.

In 63F09 mode, EXG and TFR operands are modified to exchange or transfer new Q and DS registers.

The following table lists the processor instructions and cycle counts for the MC6809, HD6309, and 63F09.

Base page ($00)

Opcodes $00-$0F

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
NEG	2	$00	Direct	6	5	5	5
OIM	3	$01	Direct	-	6	6	6
AIM	3	$02	Direct	-	6	6	6
COM	2	$03	Direct	6	5	5	5
LSR	2	$04	Direct	6	5	5	5
EIM	3	$05	Direct	-	6	6	6
ROR	2	$06	Direct	6	5	5	5
ASR	2	$07	Direct	6	5	5	5
ASL	2	$08	Direct	6	5	5	5
LSL	2	$08	Direct	6	5	5	5
ROL	2	$09	Direct	6	5	5	5
DEC	2	$0A	Direct	6	5	5	5
TIM	3	$0B	Direct	-	6	4	4
INC	2	$0C	Direct	6	5	5	5
TST	2	$0D	Direct	6	4	3	3
JMP	2	$0E	Direct	3	2	3	3
CLR	2	$0F	Direct	6	5	4	4

Opcodes $10-$1F

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
NOP	1	$12	Inherent	2	1	1	1
SYNC	1	$13	Inherent	2	1	1	1
SEXW	1	$14	Inherent	-	4	1	1
HCF	1	$15	Inherent	1	1	1	1
LBRA	3/5	$16	Relative	5	4	4	6
LBSR	3/5	$17	Relative	9	7	6	10
DAA	1	$19	Inherent	2	1	1	1
ORCC	2	$1A	Immediate	3	2	2	2
ANDCC	2	$1C	Immediate	3	3	2	2
SEX	1	$1D	Inherent	2	1	1	1
EXG	2	$1E	Inter-register	8	5	4	4
TFR	2	$1F	Inter-register	6	4	2	2

Opcodes $20-$2F

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
BRA	2	$20	Relative 8-bit	3	3	3	3
BRN	2	$21	Relative 8-bit	3	3	2	2
BHI	2	$22	Relative 8-bit	3	3	2	2
BLS	2	$23	Relative 8-bit	3	3	2	2
BHS	2	$24	Relative 8-bit	3	3	2	2
BCC	2	$24	Relative 8-bit	3	3	2	2
BLO	2	$25	Relative 8-bit	3	3	2	2
BCS	2	$25	Relative 8-bit	3	3	2	2
BNE	2	$26	Relative 8-bit	3	3	2	2
BEQ	2	$27	Relative 8-bit	3	3	2	2
BVC	2	$28	Relative 8-bit	3	3	2	2
BVS	2	$29	Relative 8-bit	3	3	2	2
BPL	2	$2A	Relative 8-bit	3	3	2	2
BMI	2	$2B	Relative 8-bit	3	3	2	2
BGE	2	$2C	Relative 8-bit	3	3	2	2
BLT	2	$2D	Relative 8-bit	3	3	2	2
BGT	2	$2E	Relative 8-bit	3	3	2	2
BLE	2	$2F	Relative 8-bit	3	3	2	2

Opcodes $30-$3F

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
LEAX	2	$30	Indexed	4	4	3	3
LEAX	4/6	$30	Indexed indirect	7	7	8	10
LEAY	2	$31	Indexed	4	4	3	3
LEAY	4/6	$31	Indexed indirect	7	7	8	10
LEAS	2	$32	Indexed	4	4	3	3
LEAS	4/6	$32	Indexed indirect	7	7	8	10
LEAU	2	$33	Indexed	4	4	3	3
LEAU	4/6	$33	Indexed indirect	7	7	8	10
PSHS	2/3	$34	Register list	5	4	3	4
PULS	2/3	$35	Register list	5	4	3	4
PSHU	2/3	$36	Register list	5	4	3	4
PULU	2/3	$37	Register list	5	4	3	4
ENI	1	$38	Inherent	-	-	-	1
RTS	1	$39	Inherent	5	5	3	5
ABX	1	$3A	Inherent	3	1	1	1
RTI	1	$3B	Inherent	6	17	4	10
CWAI	2/5	$3C	Immediate	22	20	16	39
MUL	1	$3D	Inherent	11	10	11	11
DII	1	$3E	Inherent	-	-	-	1
SWI	1	$3F	Inherent	19	21	17	37

Opcodes $40-$4F

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
NEGA	1	$40	Inherent	2	1	1	1
LOCK	1	$41	Inherent	-	-	-	2
COMA	1	$43	Inherent	2	1	1	1
LSRA	1	$44	Inherent	2	1	1	1
RORA	1	$46	Inherent	2	1	1	1
ASRA	1	$47	Inherent	2	1	1	1
ASLA	1	$48	Inherent	2	1	1	1
LSLA	1	$48	Inherent	2	1	1	1
ROLA	1	$49	Inherent	2	1	1	1
DECA	1	$4A	Inherent	2	1	1	1
INCA	1	$4C	Inherent	2	1	1	1
TSTA	1	$4D	Inherent	2	1	1	1
CLRA	1	$4F	Inherent	2	1	1	1

Opcodes $50-$5F

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
NEGB	1	$50	Inherent	2	1	1	1
UNLOCK	1	$51	Inherent	-	-	-	1
COMB	1	$53	Inherent	2	1	1	1
LSRB	1	$54	Inherent	2	1	1	1
RORB	1	$56	Inherent	2	1	1	1
ASRB	1	$57	Inherent	2	1	1	1
ASLB	1	$58	Inherent	2	1	1	1
LSLB	1	$58	Inherent	2	1	1	1
ROLB	1	$59	Inherent	2	1	1	1
DECB	1	$5A	Inherent	2	1	1	1
INCB	1	$5C	Inherent	2	1	1	1
TSTB	1	$5D	Inherent	2	1	1	1
CLRB	1	$5F	Inherent	2	1	1	1

Opcodes $60-$6F

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
NEG	2	$60	Indexed	6	6	6	6
NEG	4/6	$60	Indexed indirect	9	9	8	10
OIM	3	$61	Indexed	-	7	7	7
AIM	3	$62	Indexed	-	7	7	7
COM	2	$63	Indexed	6	6	6	6
COM	4/6	$63	Indexed indirect	9	9	8	10
LSR	2	$64	Indexed	6	6	6	6
LSR	2/4	$64	Indexed indirect	9	9	8	6
EIM	3	$65	Indexed	-	7	7	7
ROR	2	$66	Indexed	6	6	6	6
ROR	4/6	$66	Indexed indirect	9	9	8	10
ASR	2	$67	Indexed	6	6	6	6
ASR	4/6	$67	Indexed indirect	9	9	8	10
ASL	2	$68	Indexed	6	6	6	6
ASL	4/6	$68	Indexed indirect	9	9	8	10
LSL	2	$68	Indexed	6	6	6	6
LSL	4/6	$68	Indexed indirect	9	9	8	10
ROL	2	$69	Indexed	6	6	6	6
ROL	4/6	$69	Indexed indirect	9	9	8	10
DEC	2	$6A	Indexed	6	6	6	6
DEC	4/6	$6A	Indexed indirect	9	9	8	10
TIM	3	$6B	Indexed	-	7	5	5
INC	2	$6C	Indexed	6	6	6	6
INC	4/6	$6C	Indexed indirect	9	9	8	10
TST	2	$6D	Indexed	6	5	6	6
TST	4/6	$6D	Indexed indirect	9	8	8	10
JMP	2	$6E	Indexed	3	3	4	4
JMP	4/6	$6E	Indexed indirect	6	6	9	11
CLR	2	$6F	Indexed	6	6	6	6
CLR	4/6	$6F	Indexed indirect	9	9	8	10

Opcodes $70-$7F

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
NEG	3/5	$70	Extended	7	6	6	8
OIM	4/6	$71	Extended	-	7	6	8
AIM	4/6	$72	Extended	-	7	6	8
COM	3/5	$73	Extended	7	6	6	8
LSR	3/5	$74	Extended	7	6	6	8
EIM	4/6	$75	Extended	-	7	6	8
ROR	3/5	$76	Extended	7	6	6	8
ASR	3/5	$77	Extended	7	6	6	8
ASL	3/5	$78	Extended	7	6	6	8
LSL	3/5	$78	Extended	7	6	6	8
ROL	3/5	$79	Extended	7	6	6	8
DEC	3/5	$7A	Extended	7	6	6	8
TIM	4/6	$7B	Extended	-	7	4	6
INC	3/5	$7C	Extended	7	6	6	8
TST	3/5	$7D	Extended	7	5	6	8
JMP	3/5	$7E	Extended	4	3	4	6
CLR	3/5	$7F	Extended	7	6	6	8

Opcodes $80-$8F

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
SUBA	2	$80	Immediate	2	2	2	2
CMPA	2	$81	Immediate	2	2	2	2
SBCA	2	$82	Immediate	2	2	2	2
SUBD	3	$83	Immediate	4	3	3	3
ANDA	2	$84	Immediate	2	2	2	2
BITA	2	$85	Immediate	2	2	2	2
LDA	2	$86	Immediate	2	2	2	2
EORA	2	$88	Immediate	2	2	2	2
ADCA	2	$89	Immediate	2	2	2	2
ORA	2	$8A	Immediate	2	2	2	2
ADDA	2	$8B	Immediate	2	2	2	2
CMPX	3/5	$8C	Immediate	4	3	3	5
BSR	2	$8D	Relative 8-bit	7	6	5	5
LDX	3/5	$8E	Immediate	3	3	3	5

Opcodes $90-$9F

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
SUBA	2	$90	Direct	4	3	3	3
CMPA	2	$91	Direct	4	3	3	3
SBCA	2	$92	Direct	4	3	3	3
SUBD	2	$93	Direct	6	4	4	4
ANDA	2	$94	Direct	4	3	3	3
BITA	2	$95	Direct	4	3	3	3
LDA	2	$96	Direct	4	3	3	3
STA	2	$97	Direct	4	3	4	4
EORA	2	$98	Direct	4	3	3	3
ADCA	2	$99	Direct	4	3	3	3
ORA	2	$9A	Direct	4	3	3	3
ADDA	2	$9B	Direct	4	3	3	3
CMPX	2	$9C	Direct	6	4	4	6
JSR	2	$9D	Direct	7	6	4	6
LDX	2	$9E	Direct	5	4	4	6
STX	2	$9F	Direct	5	4	5	7

Opcodes $A0-$AF

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
SUBA	2	$A0	Indexed	4	4	4	4
SUBA	4/6	$A0	Indexed indirect	7	7	6	8
CMPA	2	$A1	Indexed	4	4	4	4
CMPA	4/6	$A1	Indexed indirect	7	7	9	11
SBCA	2	$A2	Indexed	4	4	4	4
SBCA	4/6	$A2	Indexed indirect	7	7	9	11
SUBD	2	$A3	Indexed	6	5	5	5
SUBD	4/6	$A3	Indexed indirect	9	8	10	12
ANDA	2	$A4	Indexed	4	4	4	4
ANDA	4/6	$A4	Indexed indirect	7	7	9	11
BITA	2	$A5	Indexed	4	4	4	4
BITA	4/6	$A5	Indexed indirect	7	7	9	11
LDA	2	$A6	Indexed	4	4	4	4
LDA	4/6	$A6	Indexed indirect	7	7	9	11
STA	2	$A7	Indexed	4	4	5	5
STA	4/6	$A7	Indexed indirect	7	7	10	12
EORA	2	$A8	Indexed	4	4	4	4
EORA	4/6	$A8	Indexed indirect	7	7	9	11
ADCA	2	$A9	Indexed	4	4	4	4
ADCA	4/6	$A9	Indexed indirect	7	7	9	11
ORA	2	$AA	Indexed	4	4	4	4
ORA	4/6	$AA	Indexed indirect	7	7	9	11
ADDA	2	$AB	Indexed	4	4	4	4
ADDA	4/6	$AB	Indexed indirect	7	7	9	11
CMPX	2	$AC	Indexed	6	5	5	7
CMPX	4/6	$AC	Indexed indirect	9	9	10	14
JSR	2	$AD	Indexed	7	6	5	7
JSR	4/6	$AD	Indexed indirect	10	9	10	14
LDX	2	$AE	Indexed	5	5	5	7
LDX	4/6	$AE	Indexed indirect	8	8	10	14
STX	2	$AF	Indexed	5	5	6	8
STX	4/6	$AF	Indexed indirect	8	8	11	15

Opcodes $B0-$BF

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
SUBA	3/5	$B0	Extended	5	4	4	6
CMPA	3/5	$B1	Extended	5	4	4	6
SBCA	3/5	$B2	Extended	5	4	4	6
SUBD	3/5	$B3	Extended	7	5	5	7
ANDA	3/5	$B4	Extended	5	4	4	6
BITA	3/5	$B5	Extended	5	4	4	6
LDA	3/5	$B6	Extended	5	4	4	6
STA	3/5	$B7	Extended	5	4	5	7
EORA	3/5	$B8	Extended	5	4	4	6
ADCA	3/5	$B9	Extended	5	4	4	6
ORA	3/5	$BA	Extended	5	4	4	6
ADDA	3/5	$BB	Extended	5	4	4	6
CMPX	3/5	$BC	Extended	7	5	5	9
JSR	3/5	$BD	Extended	8	7	5	9
LDX	3/5	$BE	Extended	6	5	5	9
STX	3/5	$BF	Extended	6	5	6	10

Opcodes $C0-$CF

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
SUBB	2	$C0	Immediate	2	2	2	2
CMPB	2	$C1	Immediate	2	2	2	2
SBCB	2	$C2	Immediate	2	2	2	2
ADDD	3	$C3	Immediate	4	3	3	3
ANDB	2	$C4	Immediate	2	2	2	2
BITB	2	$C5	Immediate	2	2	2	2
LDB	2	$C6	Immediate	2	2	2	2
EORB	2	$C8	Immediate	2	2	2	2
ADCB	2	$C9	Immediate	2	2	2	2
ORB	2	$CA	Immediate	2	2	2	2
ADDB	2	$CB	Immediate	2	2	2	2
LDD	3	$CC	Immediate	3	3	3	3
LDQ	5	$CD	Immediate	5	5	5	5
LDU	3/5	$CE	Immediate	3	3	3	5

Opcodes $D0-$DF

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
SUBB	2	$D0	Direct	4	3	3	3
CMPB	2	$D1	Direct	4	3	3	3
SBCB	2	$D2	Direct	4	3	3	3
ADDD	2	$D3	Direct	6	4	4	4
ANDB	2	$D4	Direct	4	3	3	3
BITB	2	$D5	Direct	4	3	3	3
LDB	2	$D6	Direct	4	3	3	3
STB	2	$D7	Direct	4	3	4	4
EORB	2	$D8	Direct	4	3	3	3
ADCB	2	$D9	Direct	4	3	3	3
ORB	2	$DA	Direct	4	3	3	3
ADDB	2	$DB	Direct	4	3	3	3
LDD	2	$DC	Direct	5	4	4	4
STD	2	$DD	Direct	5	4	5	5
LDU	2	$DE	Direct	5	4	4	6
STU	2	$DF	Direct	5	4	5	7

Opcodes $E0-$EF

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
SUBB	2	$E0	Indexed	4	4	4	4
SUBB	4/6	$E0	Indexed indirect	7	7	6	8
CMPB	2	$E1	Indexed	4	4	4	4
CMPB	4/6	$E1	Indexed indirect	7	7	9	11
SBCB	2	$E2	Indexed	4	4	4	4
SBCB	4/6	$E2	Indexed indirect	7	7	9	11
ADDD	2	$E3	Indexed	6	5	5	5
ADDD	4/6	$E3	Indexed indirect	9	8	10	12
ANDB	2	$E4	Indexed	4	4	4	4
ANDB	4/6	$E4	Indexed indirect	7	7	9	11
BITB	2	$E5	Indexed	4	4	4	4
BITB	4/6	$E5	Indexed indirect	7	7	9	11
LDB	2	$E6	Indexed	4	4	4	4
LDB	4/6	$E6	Indexed indirect	7	7	9	11
STB	2	$E7	Indexed	4	4	5	5
STB	4/6	$E7	Indexed indirect	7	7	10	12
EORB	2	$E8	Indexed	4	4	4	4
EORB	4/6	$E8	Indexed indirect	7	7	9	11
ADCB	2	$E9	Indexed	4	4	4	4
ADCB	4/6	$E9	Indexed indirect	7	7	9	11
ORB	2	$EA	Indexed	4	4	4	4
ORB	4/6	$EA	Indexed indirect	7	7	9	11
ADDB	2	$EB	Indexed	4	4	4	4
ADDB	4/6	$EB	Indexed indirect	7	7	9	11
LDD	2	$EC	Indexed	5	5	5	5
LDD	4/6	$EC	Indexed indirect	8	8	10	12
STD	2	$ED	Indexed	5	5	5	6
STD	4/6	$ED	Indexed indirect	8	8	11	13
LDU	2	$EE	Indexed	5	5	5	7
LDU	4/6	$EE	Indexed indirect	8	8	10	14
STU	2	$EF	Indexed	5	5	5	8
STU	4/6	$EF	Indexed indirect	8	8	11	15

Opcodes $F0-$FF

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
SUBB	3/5	$F0	Extended	5	4	4	6
CMPB	3/5	$F1	Extended	5	4	4	6
SBCB	3/5	$F2	Extended	5	4	4	6
ADDD	3/5	$F3	Extended	7	5	5	7
ANDB	3/5	$F4	Extended	5	4	4	6
BITB	3/5	$F5	Extended	5	4	4	6
LDB	3/5	$F6	Extended	5	4	4	6
STB	3/5	$F7	Extended	5	4	5	7
EORB	3/5	$F8	Extended	5	4	4	6
ADCB	3/5	$F9	Extended	5	4	4	6
ORB	3/5	$FA	Extended	5	4	4	6
ADDB	3/5	$FB	Extended	5	4	4	6
LDD	3/5	$FC	Extended	6	5	5	7
STD	3/5	$FD	Extended	6	5	5	8
LDU	3/5	$FE	Extended	6	5	5	9
STU	3/5	$FF	Extended	6	5	6	10

Prefix $10 ($10)

Opcodes $1020-$102F

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
LBRN	4/6	$1021	Relative	5	5	4	6
LBHI	4/6	$1022	Relative	5	5	4	6
LBLS	4/6	$1023	Relative	5	5	4	6
LBHS	4/6	$1024	Relative	5	5	4	6
LBCC	4/6	$1024	Relative	5	5	4	6
LBCS	4/6	$1025	Relative	5	5	4	6
LBLO	4/6	$1025	Relative	5	5	4	6
LBNE	4/6	$1026	Relative	5	5	4	6
LBEQ	4/6	$1027	Relative	5	5	4	6
LBVC	4/6	$1028	Relative	5	5	4	6
LBVS	4/6	$1029	Relative	5	5	4	6
LBPL	4/6	$102A	Relative	5	5	4	6
LBMI	4/6	$102B	Relative	5	5	4	6
LBGE	4/6	$102C	Relative	5	5	4	6
LBLT	4/6	$102D	Relative	5	5	4	6
LBGT	4/6	$102E	Relative	5	5	4	6
LBLE	4/6	$102F	Relative	5	5	4	6

Opcodes $1030-$103F

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
ADDR	3	$1030	Inter-register	-	4	3	3
ADCR	3	$1031	Inter-register	-	4	3	3
SUBR	3	$1032	Inter-register	-	4	3	3
SBCR	3	$1033	Inter-register	-	4	3	3
ANDR	3	$1034	Inter-register	-	4	3	3
ORR	3	$1035	Inter-register	-	4	3	3
EORR	3	$1036	Inter-register	-	4	3	3
CMPR	3	$1037	Inter-register	-	4	3	3
PSHSW	2	$1038	Inherent	-	6	5	-
PULSW	2	$1039	Inherent	-	6	4	-
PSHUW	2	$103A	Inherent	-	6	5	-
PULUW	2	$103B	Inherent	-	6	4	-
SWI2	2	$103F	Inherent	20	22	18	38

Opcodes $1040-$104F

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
NEGD	2	$1040	Inherent	-	2	2	2
ANDW	4	$1041	Immediate	-	-	-	5
ORW	4	$1042	Immediate	-	-	-	5
COMD	2	$1043	Inherent	-	2	2	2
LSRD	2	$1044	Inherent	-	2	2	2
EORW	4	$1045	Immediate	-	-	-	5
RORD	2	$1046	Inherent	-	2	2	2
ASRD	2	$1047	Inherent	-	2	2	2
ASLD	2	$1048	Inherent	-	2	2	2
LSLD	2	$1048	Inherent	-	2	2	2
ROLD	2	$1049	Inherent	-	2	2	2
DECD	2	$104A	Inherent	-	2	2	2
ADCW	4	$104B	Immediate	-	-	-	5
INCD	2	$104C	Inherent	-	2	2	2
TSTD	2	$104D	Inherent	-	2	2	2
SBCW	4	$104E	Immediate	-	-	-	5
CLRD	2	$104F	Inherent	-	2	2	2

Opcodes $1050-$105F

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
NEGW	2	$1050	Inherent	-	-	-	2
ANDW	3	$1051	Direct	-	-	-	4
ORW	3	$1052	Direct	-	-	-	4
COMW	2	$1053	Inherent	-	2	2	2
LSRW	2	$1054	Inherent	-	2	2	2
EORW	3	$1055	Direct	-	-	-	4
RORW	2	$1056	Inherent	-	2	2	2
ASRW	2	$1057	Inherent	-	-	-	2
ASLW	2	$1058	Inherent	-	-	-	2
LSLW	2	$1058	Inherent	-	-	-	2
ROLW	2	$1059	Inherent	-	2	2	2
DECW	2	$105A	Inherent	-	2	2	2
ADCW	3	$105B	Direct	-	-	-	4
INCW	2	$105C	Inherent	-	2	2	2
TSTW	2	$105D	Inherent	-	2	2	2
SBCW	3	$105E	Direct	-	-	-	4
CLRW	2	$105F	Inherent	-	2	2	2

Opcodes $1060-$106F

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
NEGQ	2	$1060	Inherent	-	-	-	2
ANDW	3	$1061	Indexed	-	-	-	5
ANDW	5	$1061	Indexed indirect	-	-	-	13
ORW	3	$1062	Indexed	-	-	-	5
ORW	5	$1062	Indexed indirect	-	-	-	13
COMQ	2	$1063	Inherent	-	-	-	2
LSRQ	2	$1064	Inherent	-	-	-	2
EORW	3	$1065	Indexed	-	-	-	5
EORW	5	$1065	Indexed indirect	-	-	-	13
RORQ	2	$1066	Inherent	-	-	-	2
ASRQ	2	$1067	Inherent	-	-	-	2
ASLQ	2	$1068	Inherent	-	-	-	2
LSLQ	2	$1068	Inherent	-	-	-	2
ROLQ	2	$1069	Inherent	-	-	-	2
DECQ	2	$106A	Inherent	-	-	-	2
ADCW	3	$106B	Indexed	-	-	-	5
ADCW	5	$106B	Indexed indirect	-	-	-	13
INCQ	2	$106C	Inherent	-	-	-	2
TSTQ	2	$106D	Inherent	-	-	-	2
SBCW	3	$106E	Indexed	-	-	-	5
SBCW	5	$106E	Indexed indirect	-	-	-	13
CLRQ	2	$106F	Inherent	-	-	-	2

Opcodes $1070-$107F

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
NEGV	2	$1070	Inherent	-	-	-	2
ANDW	6	$1071	Extended	-	-	-	8
ORW	6	$1072	Extended	-	-	-	8
COMV	2	$1073	Inherent	-	-	-	2
LSRV	2	$1074	Inherent	-	-	-	2
EORW	6	$1075	Extended	-	-	-	8
RORV	2	$1076	Inherent	-	-	-	2
ASRV	2	$1077	Inherent	-	-	-	2
ASLV	2	$1078	Inherent	-	-	-	2
LSLV	2	$1078	Inherent	-	-	-	2
ROLV	2	$1079	Inherent	-	-	-	2
DECV	2	$107A	Inherent	-	-	-	2
ADCW	6	$107B	Extended	-	-	-	8
INCV	2	$107C	Inherent	-	-	-	2
TSTV	2	$107D	Inherent	-	-	-	2
SBCW	6	$107E	Extended	-	-	-	8
CLRV	2	$107F	Inherent	-	-	-	2

Opcodes $1080-$108F

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
SUBW	4	$1080	Immediate	-	4	4	4
CMPW	4	$1081	Immediate	-	4	4	4
SBCD	4	$1082	Immediate	-	4	4	4
CMPD	4	$1083	Immediate	5	4	4	4
ANDD	4	$1084	Immediate	-	4	4	4
BITD	4	$1085	Immediate	-	4	4	4
LDW	4	$1086	Immediate	-	4	4	4
EORD	4	$1088	Immediate	-	4	4	4
ADCD	4	$1089	Immediate	-	4	4	4
ORD	4	$108A	Immediate	-	4	4	4
ADDW	4	$108B	Immediate	-	4	4	4
CMPY	4/6	$108C	Immediate	5	4	4	6
BITW	4	$108D	Immediate	-	-	-	4
LDY	4/6	$108E	Immediate	5	4	4	6

Opcodes $1090-$109F

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
SUBW	3	$1090	Direct	-	5	5	5
CMPW	3	$1091	Direct	-	5	5	5
SBCD	3	$1092	Direct	-	5	5	5
CMPD	3	$1093	Direct	7	5	7	7
ANDD	3	$1094	Direct	-	5	5	5
BITD	3	$1095	Direct	-	5	5	5
LDW	3	$1096	Direct	-	5	5	5
STW	3	$1097	Direct	-	5	6	6
EORD	3	$1098	Direct	-	5	5	5
ADCD	3	$1099	Direct	-	5	5	5
ORD	3	$109A	Direct	-	5	5	5
ADDW	3	$109B	Direct	-	5	5	5
CMPY	3	$109C	Direct	7	5	5	7
BITW	3	$109D	Direct	-	-	-	7
LDY	3	$109E	Direct	6	5	5	7
STY	3	$109F	Direct	6	5	6	8

Opcodes $10A0-$10AF

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
SUBW	3	$10A0	Indexed	-	6	6	6
SUBW	5/7	$10A0	Indexed indirect	-	7	11	13
CMPW	3	$10A1	Indexed	-	6	6	6
CMPW	5/7	$10A1	Indexed indirect	-	7	11	13
SBCD	3	$10A2	Indexed	-	6	6	6
SBCD	5/7	$10A2	Indexed indirect	-	7	6	11
CMPD	3	$10A3	Indexed	7	6	6	6
CMPD	5/7	$10A3	Indexed indirect	8	7	11	13
ANDD	3	$10A4	Indexed	-	6	6	6
ANDD	5/7	$10A4	Indexed indirect	-	7	6	11
BITD	3	$10A5	Indexed	-	6	6	6
BITD	5/7	$10A5	Indexed indirect	-	7	6	11
LDW	3	$10A6	Indexed	-	6	6	6
LDW	5/7	$10A6	Indexed indirect	-	7	11	13
STW	3	$10A7	Indexed	-	6	6	7
STW	5/7	$10A7	Indexed indirect	-	7	12	14
EORD	3	$10A8	Indexed	-	6	6	6
EORD	5/7	$10A8	Indexed indirect	-	7	6	11
ADCD	3	$10A9	Indexed	-	6	6	6
ADCD	5/7	$10A9	Indexed indirect	-	7	6	11
ORD	3	$10AA	Indexed	-	6	6	6
ORD	5/7	$10AA	Indexed indirect	-	7	6	11
ADDW	3	$10AB	Indexed	-	6	6	6
ADDW	5/7	$10AB	Indexed indirect	-	7	11	13
CMPY	3	$10AC	Indexed	7	6	7	8
CMPY	5/7	$10AC	Indexed indirect	8	7	11	15
BITW	3	$10AD	Indexed	-	-	-	6
BITW	7	$10AD	Indexed indirect	-	-	-	13
LDY	3	$10AE	Indexed	6	6	7	8
LDY	5/7	$10AE	Indexed indirect	-	7	11	15
STY	3	$10AF	Indexed	6	6	7	9
STY	5/7	$10AF	Indexed indirect	-	7	12	16

Opcodes $10B0-$10BF

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
SUBW	4/6	$10B0	Extended	-	6	6	8
CMPW	4/6	$10B1	Extended	-	6	6	8
SBCD	4/6	$10B2	Extended	-	6	6	8
CMPD	4/6	$10B3	Extended	8	6	6	8
ANDD	4/6	$10B4	Extended	-	6	6	8
BITD	4/6	$10B5	Extended	-	6	6	8
LDW	4/6	$10B6	Extended	-	6	6	8
STW	4/6	$10B7	Extended	-	6	6	9
EORD	4/6	$10B8	Extended	-	6	6	8
ADCD	4/6	$10B9	Extended	-	6	6	8
ORD	4/6	$10BA	Extended	-	6	6	8
ADDW	4/6	$10BB	Extended	-	6	6	8
CMPY	4/6	$10BC	Extended	8	6	6	10
BITW	6	$10BD	Extended	-	-	-	8
LDY	4/6	$10BE	Extended	7	6	6	10
STY	4/6	$10BF	Extended	7	6	7	11

Opcodes $10C0-$10CF

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
ANDQ	6	$10C0	Immediate	-	-	-	6
BITQ	6	$10C1	Immediate	-	-	-	6
EORQ	6	$10C2	Immediate	-	-	-	6
ORQ	6	$10C3	Immediate	-	-	-	6
LDDP	3	$10C6	Immediate	-	-	-	3
LDDS	4	$10C8	Immediate	-	-	-	4
LDV	6	$10CA	Immediate	-	-	-	6
LDS	4/6	$10CE	Immediate	4	4	4	6

Opcodes $10D0-$10DF

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
ANDQ	3	$10D0	Direct	-	-	-	4
BITQ	3	$10D1	Direct	-	-	-	4
EORQ	3	$10D2	Direct	-	-	-	4
ORQ	3	$10D3	Direct	-	-	-	4
LDDP	3	$10D6	Direct	-	-	-	4
STDP	3	$10D7	Direct	-	-	-	4
LDDS	3	$10D8	Direct	-	-	-	5
STDS	3	$10D9	Direct	-	-	-	5
LDV	3	$10DA	Direct	-	-	-	7
STV	3	$10DB	Direct	-	-	-	8
LDQ	3	$10DC	Direct	-	7	7	7
STQ	3	$10DD	Direct	-	7	8	8
LDS	3	$10DE	Direct	6	5	5	7
STS	3	$10DF	Direct	6	5	5	7

Opcodes $10E0-$10EF

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
ANDQ	3	$10E0	Indexed	-	-	-	7
ANDQ	7	$10E0	Indexed indirect	-	-	-	11
BITQ	3	$10E1	Indexed	-	-	-	7
BITQ	7	$10E1	Indexed indirect	-	-	-	11
EORQ	7	$10E2	Indexed	-	-	-	11
EORQ	7	$10E2	Indexed indirect	-	-	-	11
ORQ	7	$10E3	Indexed	-	-	-	7
ORQ	7	$10E3	Indexed indirect	-	-	-	11
LDDP	3	$10E6	Indexed	-	-	-	5
LDDP	7	$10E6	Indexed indirect	-	-	-	9
STDP	3	$10E7	Indexed	-	-	-	5
STDP	7	$10E7	Indexed indirect	-	-	-	9
LDDS	3	$10E8	Indexed	-	-	-	7
LDDS	7	$10E8	Indexed indirect	-	-	-	11
STDS	3	$10E9	Indexed	-	-	-	7
STDS	7	$10E9	Indexed indirect	-	-	-	11
LDV	3	$10EA	Indexed	-	-	-	7
LDV	7	$10EA	Indexed indirect	-	-	-	15
STV	3	$10EB	Indexed	-	-	-	9
STV	7	$10EB	Indexed indirect	-	-	-	16
LDQ	3	$10EC	Indexed	-	8	8	8
LDQ	7	$10EC	Indexed indirect	-	11	15	15
STQ	3	$10ED	Indexed	-	8	9	9
STQ	7	$10ED	Indexed indirect	-	11	16	16
LDS	3	$10EE	Indexed	6	6	6	8
LDS	5/7	$10EE	Indexed indirect	9	9	11	15
STS	3	$10EF	Indexed	6	6	7	9
STS	5/7	$10EF	Indexed indirect	9	9	12	16

Opcodes $10F0-$10FF

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
ANDQ	6	$10F0	Extended	-	-	-	10
BITQ	6	$10F1	Extended	-	-	-	10
EORQ	6	$10F2	Extended	-	-	-	10
ORQ	6	$10F3	Extended	-	-	-	10
LDDP	6	$10F6	Extended	-	-	-	7
STDP	6	$10F7	Extended	-	-	-	7
LDDS	6	$10F8	Extended	-	-	-	8
STDS	6	$10F9	Extended	-	-	-	8
LDV	6	$10FA	Extended	-	-	-	10
STV	6	$10FB	Extended	-	-	-	11
LDQ	4/6	$10FC	Extended	-	8	8	10
STQ	4/6	$10FD	Extended	-	8	8	11
LDS	4/6	$10FE	Extended	7	6	6	10
STS	4/6	$10FF	Extended	7	6	6	10

Prefix $11 ($11)

Opcodes $1130-$113F

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
BAND	4	$1130	Inter-register	-	6	7	7
BIAND	4	$1131	Inter-register	-	6	7	7
BOR	4	$1132	Inter-register	-	6	7	7
BIOR	4	$1133	Inter-register	-	6	7	7
BEOR	4	$1134	Inter-register	-	6	7	7
BIEOR	4	$1135	Inter-register	-	6	7	7
LDBT	4	$1136	Inter-register	-	6	7	7
STBT	4	$1137	Inter-register	-	7	9	9
TFM_II	3	$1138	Inter-register	-	6	4	4
TFM_DD	3	$1139	Inter-register	-	6	4	4
TFM_ID	3	$113A	Inter-register	-	6	4	4
TFM_DI	3	$113B	Inter-register	-	6	4	4
BITMD	3	$113C	Immediate	-	4	4	4
LDMD	3	$113D	Immediate	-	5	3	3
SWI3	2	$113F	Inherent	20	22	18	38

Opcodes $1140-$114F

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
NEGE	2	$1140	Inherent	-	-	-	2
ADDV	6	$1141	Immediate	-	-	-	6
SUBV	6	$1142	Immediate	-	-	-	6
COME	2	$1143	Inherent	-	2	2	2
LSRE	2	$1144	Inherent	-	-	-	2
CMPV	6	$1145	Immediate	-	-	-	6
RORE	2	$1146	Inherent	-	-	-	2
ASRE	2	$1147	Inherent	-	-	-	2
ASLE	2	$1148	Inherent	-	-	-	2
LSLE	2	$1148	Inherent	-	-	-	2
ROLE	2	$1149	Inherent	-	-	-	2
DECE	2	$114A	Inherent	-	2	2	2
ADCV	6	$114B	Immediate	-	-	-	6
INCE	2	$114C	Inherent	-	2	2	2
TSTE	2	$114D	Inherent	-	2	2	2
SBCV	6	$114E	Immediate	-	-	-	6
CLRE	2	$114F	Inherent	-	2	2	2

Opcodes $1150-$115F

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
NEGF	2	$1150	Inherent	-	-	-	2
ADDV	3	$1151	Direct	-	-	-	4
SUBV	3	$1152	Direct	-	-	-	4
COMF	2	$1153	Inherent	-	2	2	2
LSRF	2	$1154	Inherent	-	-	-	2
CMPV	3	$1155	Direct	-	-	-	4
RORF	2	$1156	Inherent	-	-	-	2
ASRF	2	$1157	Inherent	-	-	-	2
ASLF	2	$1158	Inherent	-	-	-	2
LSLF	2	$1158	Inherent	-	-	-	2
ROLF	2	$1159	Inherent	-	-	-	2
DECF	2	$115A	Inherent	-	2	2	2
ADCV	3	$115B	Direct	-	-	-	4
INCF	2	$115C	Inherent	-	2	2	2
TSTF	2	$115D	Inherent	-	2	2	2
SBCV	3	$115E	Direct	-	-	-	4
CLRF	2	$115F	Inherent	-	2	2	2

Opcodes $1160-$116F

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
ADDV	3	$1161	Indexed	-	-	-	8
ADDV	7	$1161	Indexed indirect	-	-	-	15
SUBV	3	$1162	Indexed	-	-	-	8
SUBV	7	$1162	Indexed indirect	-	-	-	15
CMPV	3	$1165	Indexed	-	-	-	8
CMPV	7	$1165	Indexed indirect	-	-	-	15
ADCV	3	$116B	Indexed	-	-	-	8
ADCV	7	$116B	Indexed indirect	-	-	-	15
SBCV	3	$116E	Indexed	-	-	-	8
SBCV	7	$116E	Indexed indirect	-	-	-	15

Opcodes $1170-$117F

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
ADDV	6	$1171	Extended	-	-	-	10
SUBV	6	$1172	Extended	-	-	-	10
CMPV	6	$1175	Extended	-	-	-	10
ADCV	6	$117B	Extended	-	-	-	10
SBCV	6	$117E	Extended	-	-	-	10

Opcodes $1180-$118F

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
SUBE	3	$1180	Immediate	-	3	3	3
CMPE	3	$1181	Immediate	-	3	3	3
SBCE	3	$1182	Immediate	-	-	-	3
CMPU	4/6	$1183	Immediate	5	4	4	6
ANDE	3	$1184	Immediate	-	-	-	3
BITE	3	$1185	Immediate	-	-	-	3
LDE	3	$1186	Immediate	-	3	3	3
EORE	3	$1188	Immediate	-	-	-	3
ADCE	3	$1189	Immediate	-	-	-	3
ORE	3	$118A	Immediate	-	-	-	3
ADDE	3	$118B	Immediate	-	3	3	3
CMPS	4/6	$118C	Immediate	5	4	4	6
DIVD	3/4	$118D	Immediate	-	25	25	39
DIVQ	4/6	$118E	Immediate	-	36	36	50
MULD	4	$118F	Immediate	-	28	22	22

Opcodes $1190-$119F

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
SUBE	3	$1190	Direct	-	4	4	4
CMPE	3	$1191	Direct	-	4	4	4
SBCE	3	$1192	Direct	-	-	-	4
CMPU	3	$1193	Direct	7	5	5	7
ANDE	3	$1194	Direct	-	-	-	4
BITE	3	$1195	Direct	-	-	-	4
LDE	3	$1196	Direct	-	4	4	4
STE	3	$1197	Direct	-	4	5	5
EORE	3	$1198	Direct	-	-	-	4
ADCE	3	$1199	Direct	-	-	-	4
ORE	3	$119A	Direct	-	-	-	4
ADDE	3	$119B	Direct	-	4	4	4
CMPS	3	$119C	Direct	7	5	5	7
DIVD	3	$119D	Direct	-	26	43	43
DIVQ	3	$119E	Direct	-	35	52	52
MULD	3	$119F	Direct	-	29	23	23

Opcodes $11A0-$11AF

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
SUBE	3	$11A0	Indexed	-	5	5	5
SUBE	5/7	$11A0	Indexed indirect	-	8	10	12
CMPE	3	$11A1	Indexed	-	5	5	5
CMPE	5/7	$11A1	Indexed indirect	-	8	10	12
SBCE	3	$11A2	Indexed	-	-	-	5
SBCE	7	$11A2	Indexed indirect	-	-	-	9
CMPU	3	$11A3	Indexed	7	6	6	8
CMPU	5/7	$11A3	Indexed indirect	10	9	11	15
ANDE	3	$11A4	Indexed	-	-	-	5
ANDE	7	$11A4	Indexed indirect	-	-	-	12
BITE	3	$11A5	Indexed	-	-	-	5
BITE	7	$11A5	Indexed indirect	-	-	-	12
LDE	3	$11A6	Indexed	-	5	5	5
LDE	5/7	$11A6	Indexed indirect	-	8	10	12
STE	3	$11A7	Indexed	-	5	5	6
STE	5/7	$11A7	Indexed indirect	-	8	11	13
EORE	3	$11A8	Indexed	-	-	-	5
EORE	7	$11A8	Indexed indirect	-	-	-	12
ADCE	3	$11A9	Indexed	-	-	-	5
ADCE	7	$11A9	Indexed indirect	-	-	-	12
ORE	3	$11AA	Indexed	-	-	-	5
ORE	7	$11AA	Indexed indirect	-	-	-	12
ADDE	3	$11AB	Indexed	-	5	5	5
ADDE	5/7	$11AB	Indexed indirect	-	8	7	9
CMPS	3	$11AC	Indexed	7	6	6	8
CMPS	5/7	$11AC	Indexed indirect	10	9	11	15
DIVD	3	$11AD	Indexed	-	27	25	43
DIVD	5/7	$11AD	Indexed indirect	-	30	27	47
DIVQ	3	$11AE	Indexed	-	36	34	52
DIVQ	5/7	$11AE	Indexed indirect	-	41	38	56
MULD	3	$11AF	Indexed	-	30	24	24
MULD	5/7	$11AF	Indexed indirect	-	33	26	28

Opcodes $11B0-$11BF

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
SUBE	4/6	$11B0	Extended	-	5	5	7
CMPE	4/6	$11B1	Extended	-	5	5	7
SBCE	6	$11B2	Extended	-	-	-	7
CMPU	4/6	$11B3	Extended	8	6	6	10
ANDE	6	$11B4	Extended	-	-	-	7
BITE	6	$11B5	Extended	-	-	-	7
LDE	4/6	$11B6	Extended	-	5	5	7
STE	4/6	$11B7	Extended	-	5	5	8
EORE	6	$11B8	Extended	-	-	-	7
ADCE	6	$11B9	Extended	-	-	-	7
ORE	6	$11BA	Extended	-	-	-	7
ADDE	4/6	$11BB	Extended	-	5	5	7
CMPS	4/6	$11BC	Extended	8	6	6	10
DIVD	4/6	$11BD	Extended	-	27	25	50
DIVQ	4/6	$11BE	Extended	-	36	27	52
MULD	4/6	$11BF	Extended	-	30	27	29

Opcodes $11C0-$11CF

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
SUBF	3	$11C0	Immediate	-	3	3	3
CMPF	3	$11C1	Immediate	-	3	3	3
SBCF	3	$11C2	Immediate	-	-	-	3
SUBQ	6	$11C3	Immediate	-	-	-	6
ANDF	3	$11C4	Immediate	-	-	-	3
BITF	3	$11C5	Immediate	-	-	-	3
LDF	3	$11C6	Immediate	-	3	3	3
EORF	3	$11C8	Immediate	-	-	-	3
ADCF	3	$11C9	Immediate	-	-	-	3
ORF	3	$11CA	Immediate	-	-	-	3
ADDF	3	$11CB	Immediate	-	3	3	3
SBCQ	6	$11CC	Immediate	-	-	-	6
DIVDU	4	$11CD	Immediate	-	-	-	39
DIVQU	6	$11CE	Immediate	-	-	-	50
MULDU	4	$11CF	Immediate	-	-	-	20

Opcodes $11D0-$11DF

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
SUBF	3	$11D0	Direct	-	4	4	4
CMPF	3	$11D1	Direct	-	4	4	4
SBCF	3	$11D2	Direct	-	-	-	4
SUBQ	3	$11D3	Direct	-	-	-	7
ANDF	3	$11D4	Direct	-	-	-	4
BITF	3	$11D5	Direct	-	-	-	4
LDF	3	$11D6	Direct	-	4	4	4
STF	3	$11D7	Direct	-	4	5	5
EORF	3	$11D8	Direct	-	-	-	4
ADCF	3	$11D9	Direct	-	-	-	4
ORF	3	$11DA	Direct	-	-	-	4
ADDF	3	$11DB	Direct	-	4	4	4
SBCQ	3	$11DC	Direct	-	-	-	7
DIVDU	3	$11DD	Direct	-	-	-	43
DIVQU	3	$11DE	Direct	-	-	-	52
MULDU	3	$11DF	Direct	-	-	-	21

Opcodes $11E0-$11EF

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
SUBF	3	$11E0	Indexed	-	5	5	5
SUBF	5/7	$11E0	Indexed indirect	-	8	10	12
CMPF	3	$11E1	Indexed	-	5	5	5
CMPF	5/7	$11E1	Indexed indirect	-	8	10	12
SBCF	3	$11E2	Indexed	-	-	-	5
SBCF	7	$11E2	Indexed indirect	-	-	-	9
SUBQ	3	$11E3	Indexed	-	-	-	6
SUBQ	7	$11E3	Indexed indirect	-	-	-	10
ANDF	3	$11E4	Indexed	-	-	-	5
ANDF	7	$11E4	Indexed indirect	-	-	-	12
BITF	3	$11E5	Indexed	-	-	-	5
BITF	7	$11E5	Indexed indirect	-	-	-	12
LDF	3	$11E6	Indexed	-	5	5	5
LDF	5/7	$11E6	Indexed indirect	-	8	10	12
STF	3	$11E7	Indexed	-	5	5	6
STF	5/7	$11E7	Indexed indirect	-	8	11	13
EORF	3	$11E8	Indexed	-	-	-	5
EORF	7	$11E8	Indexed indirect	-	-	-	12
ADCF	3	$11E9	Indexed	-	-	-	5
ADCF	7	$11E9	Indexed indirect	-	-	-	12
ORF	3	$11EA	Indexed	-	-	-	5
ORF	7	$11EA	Indexed indirect	-	-	-	12
ADDF	3	$11EB	Indexed	-	5	5	5
ADDF	5/7	$11EB	Indexed indirect	-	8	7	9
SBCQ	3	$11EC	Indexed	-	-	-	6
SBCQ	7	$11EC	Indexed indirect	-	-	-	10
DIVDU	3	$11ED	Indexed	-	-	-	43
DIVDU	7	$11ED	Indexed indirect	-	-	-	47
DIVQU	3	$11EE	Indexed	-	-	-	52
DIVQU	7	$11EE	Indexed indirect	-	-	-	56
MULDU	3	$11EF	Indexed	-	-	-	22
MULDU	7	$11EF	Indexed indirect	-	-	-	26

Opcodes $11F0-$11FF

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
SUBF	4/6	$11F0	Extended	-	5	5	7
CMPF	4/6	$11F1	Extended	-	5	5	7
SBCF	6	$11F2	Extended	-	-	-	7
SUBQ	6	$11F3	Extended	-	-	-	8
ANDF	6	$11F4	Extended	-	-	-	7
BITF	6	$11F5	Extended	-	-	-	7
LDF	4/6	$11F6	Extended	-	5	5	7
STF	4/6	$11F7	Extended	-	5	5	8
EORF	6	$11F8	Extended	-	-	-	7
ADCF	6	$11F9	Extended	-	-	-	7
ORF	6	$11FA	Extended	-	-	-	7
ADDF	4/6	$11FB	Extended	-	5	5	7
SBCQ	6	$11FC	Extended	-	-	-	8
DIVDU	6	$11FD	Extended	-	-	-	50
DIVQU	6	$11FE	Extended	-	-	-	52
MULDU	6	$11FF	Extended	-	-	-	27

Prefix $18 (FPU) ($18)

Opcodes $1800-$180F

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
SETRNE	2	$1800	Inherent	-	-	-	2
SETRTZ	2	$1801	Inherent	-	-	-	2
SETRDN	2	$1802	Inherent	-	-	-	2
SETRUP	2	$1803	Inherent	-	-	-	2
SETRMM	2	$1804	Inherent	-	-	-	2
SETDYN	2	$1805	Inherent	-	-	-	2

Opcodes $1810-$181F

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
PSHSFP	2	$1810	Inherent	-	-	-	132
PSHUFP	2	$1811	Inherent	-	-	-	132
PULSFP	2	$1812	Inherent	-	-	-	131
PULUFP	2	$1813	Inherent	-	-	-	131
TFROFP	2	$1814	Inherent	-	-	-	2
TFRFPO	2	$1815	Inherent	-	-	-	2
PSHSNFP	3	$1816	FP count (immediate)	-	-	-	8N+5
PSHUNFP	3	$1817	FP count (immediate)	-	-	-	8N+5
PULSNFP	3	$1818	FP count (immediate)	-	-	-	8N+4
PULUNFP	3	$1819	FP count (immediate)	-	-	-	8N+4

Opcodes $1820-$182F

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
BNV	3	$1820	Relative 8-bit	-	-	-	3
BDZ	3	$1821	Relative 8-bit	-	-	-	3
BOV	3	$1822	Relative 8-bit	-	-	-	3
BUN	3	$1823	Relative 8-bit	-	-	-	3
BIX	3	$1824	Relative 8-bit	-	-	-	3
LBNV	6	$1828	Relative	-	-	-	6
LBDZ	6	$1829	Relative	-	-	-	6
LBOV	6	$182A	Relative	-	-	-	6
LBUN	6	$182B	Relative	-	-	-	6
LBIX	6	$182C	Relative	-	-	-	6

Opcodes $1830-$183F

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
CVTOI2D	2	$1834	Inherent	-	-	-	9
CVTOU2D	2	$1835	Inherent	-	-	-	9
CVTOI2S	2	$1836	Inherent	-	-	-	9
CVTOU2S	2	$1837	Inherent	-	-	-	9
CVTS2OI	2	$1838	Inherent	-	-	-	9
CVTS2OU	2	$1839	Inherent	-	-	-	9
CVTD2OI	2	$183A	Inherent	-	-	-	9
CVTD2OU	2	$183B	Inherent	-	-	-	9

Opcodes $1860-$186F

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
FMADDNS	2	$1860	Inherent	-	-	-	15
FMSUBNS	2	$1861	Inherent	-	-	-	15
FNMADDNS	2	$1862	Inherent	-	-	-	15
FNMSUBNS	2	$1863	Inherent	-	-	-	15
FADDNS	2	$1864	Inherent	-	-	-	15
FSUBNS	2	$1865	Inherent	-	-	-	15
FMULNS	2	$1866	Inherent	-	-	-	15
FDIVNS	2	$1867	Inherent	-	-	-	48
FSQRTNS	2	$1868	Inherent	-	-	-	58
FSGNJNS	2	$1869	Inherent	-	-	-	9
FCMPNS	2	$186A	Inherent	-	-	-	9
FMAXNS	2	$186B	Inherent	-	-	-	9
FCLASSNS	2	$186C	Inherent	-	-	-	9

Opcodes $1870-$187F

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
FMADDND	2	$1870	Inherent	-	-	-	15
FMSUBND	2	$1871	Inherent	-	-	-	15
FNMADDND	2	$1872	Inherent	-	-	-	15
FNMSUBND	2	$1873	Inherent	-	-	-	15
FADDND	2	$1874	Inherent	-	-	-	15
FSUBND	2	$1875	Inherent	-	-	-	15
FMULND	2	$1876	Inherent	-	-	-	15
FDIVND	2	$1877	Inherent	-	-	-	48
FSQRTND	2	$1878	Inherent	-	-	-	58
FSGNJND	2	$1879	Inherent	-	-	-	9
FCMPND	2	$187A	Inherent	-	-	-	9
FMAXND	2	$187B	Inherent	-	-	-	9
FCLASSND	2	$187C	Inherent	-	-	-	9

Opcodes $1880-$188F

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
LDSFP	6	$1880	Immediate	-	-	-	6
LDDFP	10	$1881	Immediate	-	-	-	10

Opcodes $1890-$189F

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
LDSFP	3	$1890	Direct	-	-	-	7
LDDFP	3	$1891	Direct	-	-	-	11
STSFP	3	$1892	Direct	-	-	-	8
STDFP	3	$1893	Direct	-	-	-	12

Opcodes $18A0-$18AF

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
LDSFP	3	$18A0	Indexed	-	-	-	8
LDSFP	7	$18A0	Indexed indirect	-	-	-	15
LDDFP	3	$18A1	Indexed	-	-	-	12
LDDFP	7	$18A1	Indexed indirect	-	-	-	23
STSFP	3	$18A2	Indexed	-	-	-	9
STSFP	7	$18A2	Indexed indirect	-	-	-	16
STDFP	3	$18A3	Indexed	-	-	-	13
STDFP	7	$18A3	Indexed indirect	-	-	-	24

Opcodes $18B0-$18BF

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
LDSFP	6	$18B0	Extended	-	-	-	10
LDDFP	6	$18B1	Extended	-	-	-	14
STSFP	6	$18B2	Extended	-	-	-	11
STDFP	6	$18B3	Extended	-	-	-	15

Opcodes $18C0-$18CF

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
CVTD2S	2	$18C0	Inherent	-	-	-	9
CVTS2D	2	$18C1	Inherent	-	-	-	9
CVTI2D	2	$18C4	Inherent	-	-	-	9
CVTU2D	2	$18C5	Inherent	-	-	-	9
CVTI2S	2	$18C6	Inherent	-	-	-	9
CVTU2S	2	$18C7	Inherent	-	-	-	9
CVTS2I	2	$18C8	Inherent	-	-	-	9
CVTS2U	2	$18C9	Inherent	-	-	-	9
CVTD2I	2	$18CA	Inherent	-	-	-	9
CVTD2U	2	$18CB	Inherent	-	-	-	9

Opcodes $18D0-$18DF

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
DROPFP	2	$18D0	Inherent	-	-	-	2
DROP2FP	2	$18D1	Inherent	-	-	-	2
DUPFP	2	$18D2	Inherent	-	-	-	2
DUP2FP	2	$18D3	Inherent	-	-	-	2
SWAPFP	2	$18D4	Inherent	-	-	-	2
OVERFP	2	$18D5	Inherent	-	-	-	2
ROTFP	2	$18D6	Inherent	-	-	-	2
DUPNFP	3	$18D7	FP register	-	-	-	3
DROPNFP	3	$18D8	FP register	-	-	-	3
ROLLFP	3	$18D9	FP register	-	-	-	3
ROLLDFP	3	$18DA	FP register	-	-	-	3
PICKFP	3	$18DB	FP register	-	-	-	3
CLRFP	2	$18DC	Inherent	-	-	-	2
EXGFP	3	$18DD	Two FP registers	-	-	-	3

Opcodes $18E0-$18EF

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
FMADDS	2	$18E0	Inherent	-	-	-	15
FMSUBS	2	$18E1	Inherent	-	-	-	15
FNMADDS	2	$18E2	Inherent	-	-	-	15
FNMSUBS	2	$18E3	Inherent	-	-	-	15
FADDS	2	$18E4	Inherent	-	-	-	15
FSUBS	2	$18E5	Inherent	-	-	-	15
FMULS	2	$18E6	Inherent	-	-	-	15
FDIVS	2	$18E7	Inherent	-	-	-	48
FSQRTS	2	$18E8	Inherent	-	-	-	58
FSGNJS	2	$18E9	Inherent	-	-	-	9
FCMPS	2	$18EA	Inherent	-	-	-	9
FMAXS	2	$18EB	Inherent	-	-	-	9
FCLASSS	2	$18EC	Inherent	-	-	-	9

Opcodes $18F0-$18FF

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
FMADDD	2	$18F0	Inherent	-	-	-	15
FMSUBD	2	$18F1	Inherent	-	-	-	15
FNMADDD	2	$18F2	Inherent	-	-	-	15
FNMSUBD	2	$18F3	Inherent	-	-	-	15
FADDD	2	$18F4	Inherent	-	-	-	15
FSUBD	2	$18F5	Inherent	-	-	-	15
FMULD	2	$18F6	Inherent	-	-	-	15
FDIVD	2	$18F7	Inherent	-	-	-	48
FSQRTD	2	$18F8	Inherent	-	-	-	58
FSGNJD	2	$18F9	Inherent	-	-	-	9
FCMPD	2	$18FA	Inherent	-	-	-	9
FMAXD	2	$18FB	Inherent	-	-	-	9
FCLASSD	2	$18FC	Inherent	-	-	-	9

Prefix $1B ($1B)

Opcodes $1B40-$1B4F

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
NEGO	2	$1B40	Inherent	-	-	-	2
COMO	2	$1B43	Inherent	-	-	-	2
LSRO	2	$1B44	Inherent	-	-	-	2
RORO	2	$1B46	Inherent	-	-	-	2
ASRO	2	$1B47	Inherent	-	-	-	2
ASLO	2	$1B48	Inherent	-	-	-	2
LSLO	2	$1B48	Inherent	-	-	-	2
ROLO	2	$1B49	Inherent	-	-	-	2
DECO	2	$1B4A	Inherent	-	-	-	2
INCO	2	$1B4C	Inherent	-	-	-	2
TSTO	2	$1B4D	Inherent	-	-	-	2
SEXV	2	$1B4E	Inherent	-	-	-	2
CLRO	2	$1B4F	Inherent	-	-	-	2

Opcodes $1B80-$1B8F

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
SUBO	10	$1B80	Immediate	-	-	-	10
CMPO	10	$1B81	Immediate	-	-	-	10
SBCO	10	$1B82	Immediate	-	-	-	10
ANDO	10	$1B84	Immediate	-	-	-	10
BITO	10	$1B85	Immediate	-	-	-	10
LDO	10	$1B86	Immediate	-	-	-	10
EORO	10	$1B88	Immediate	-	-	-	10
ADCO	10	$1B89	Immediate	-	-	-	10
ORO	10	$1B8A	Immediate	-	-	-	10
ADDO	10	$1B8B	Immediate	-	-	-	10
MULQ	6	$1B8C	Immediate	-	-	-	40
DIVO	10	$1B8D	Immediate	-	-	-	152
DIVOU	10	$1B8E	Immediate	-	-	-	151
MULQU	6	$1B8F	Immediate	-	-	-	38

Opcodes $1B90-$1B9F

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
SUBO	3	$1B90	Direct	-	-	-	11
CMPO	3	$1B91	Direct	-	-	-	11
SBCO	3	$1B92	Direct	-	-	-	11
ANDO	3	$1B94	Direct	-	-	-	11
BITO	3	$1B95	Direct	-	-	-	11
LDO	3	$1B96	Direct	-	-	-	11
STO	3	$1B97	Direct	-	-	-	12
EORO	3	$1B98	Direct	-	-	-	11
ADCO	3	$1B99	Direct	-	-	-	11
ORO	3	$1B9A	Direct	-	-	-	11
ADDO	3	$1B9B	Direct	-	-	-	11
MULQ	3	$1B9C	Direct	-	-	-	41
DIVO	3	$1B9D	Direct	-	-	-	153
DIVOU	3	$1B9E	Direct	-	-	-	152
MULQU	3	$1B9F	Direct	-	-	-	39

Opcodes $1BA0-$1BAF

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
SUBO	3	$1BA0	Indexed	-	-	-	12
SUBO	7	$1BA0	Indexed indirect	-	-	-	19
CMPO	3	$1BA1	Indexed	-	-	-	12
CMPO	7	$1BA1	Indexed indirect	-	-	-	19
SBCO	3	$1BA2	Indexed	-	-	-	12
SBCO	7	$1BA2	Indexed indirect	-	-	-	19
ANDO	3	$1BA4	Indexed	-	-	-	12
ANDO	7	$1BA4	Indexed indirect	-	-	-	19
BITO	3	$1BA5	Indexed	-	-	-	12
BITO	7	$1BA5	Indexed indirect	-	-	-	19
LDO	3	$1BA6	Indexed	-	-	-	12
LDO	7	$1BA6	Indexed indirect	-	-	-	19
STO	3	$1BA7	Indexed	-	-	-	13
STO	7	$1BA7	Indexed indirect	-	-	-	20
EORO	3	$1BA8	Indexed	-	-	-	12
EORO	7	$1BA8	Indexed indirect	-	-	-	19
ADCO	3	$1BA9	Indexed	-	-	-	12
ADCO	7	$1BA9	Indexed indirect	-	-	-	19
ORO	3	$1BAA	Indexed	-	-	-	12
ORO	7	$1BAA	Indexed indirect	-	-	-	19
ADDO	3	$1BAB	Indexed	-	-	-	12
ADDO	7	$1BAB	Indexed indirect	-	-	-	19
MULQ	3	$1BAC	Indexed	-	-	-	42
MULQ	7	$1BAC	Indexed indirect	-	-	-	49
DIVO	3	$1BAD	Indexed	-	-	-	154
DIVO	7	$1BAD	Indexed indirect	-	-	-	165
DIVOU	3	$1BAE	Indexed	-	-	-	153
DIVOU	7	$1BAE	Indexed indirect	-	-	-	164
MULQU	3	$1BAF	Indexed	-	-	-	40
MULQU	7	$1BAF	Indexed indirect	-	-	-	47

Opcodes $1BB0-$1BBF

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
SUBO	6	$1BB0	Extended	-	-	-	14
CMPO	6	$1BB1	Extended	-	-	-	14
SBCO	6	$1BB2	Extended	-	-	-	14
ANDO	6	$1BB4	Extended	-	-	-	14
BITO	6	$1BB5	Extended	-	-	-	14
LDO	6	$1BB6	Extended	-	-	-	14
STO	6	$1BB7	Extended	-	-	-	15
EORO	6	$1BB8	Extended	-	-	-	14
ADCO	6	$1BB9	Extended	-	-	-	14
ORO	6	$1BBA	Extended	-	-	-	14
ADDO	6	$1BBB	Extended	-	-	-	14
MULQ	6	$1BBC	Extended	-	-	-	44
DIVO	6	$1BBD	Extended	-	-	-	156
DIVOU	6	$1BBE	Extended	-	-	-	155
MULQU	6	$1BBF	Extended	-	-	-	42

Opcodes $1BC0-$1BCF

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
ANDV	6	$1BC0	Immediate	-	-	-	6
BITV	6	$1BC1	Immediate	-	-	-	6
EORV	6	$1BC2	Immediate	-	-	-	6
ORV	6	$1BC3	Immediate	-	-	-	6
MULOU	10	$1BC8	Immediate	-	-	-	74
MULO	10	$1BC9	Immediate	-	-	-	76
ADCQ	6	$1BCD	Immediate	-	-	-	6
CMPQ	6	$1BCE	Immediate	-	-	-	6
ADDQ	6	$1BCF	Immediate	-	-	-	6

Opcodes $1BD0-$1BDF

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
ANDV	3	$1BD0	Direct	-	-	-	7
BITV	3	$1BD1	Direct	-	-	-	7
EORV	3	$1BD2	Direct	-	-	-	7
ORV	3	$1BD3	Direct	-	-	-	7
MULOU	3	$1BD8	Direct	-	-	-	75
MULO	3	$1BD9	Direct	-	-	-	77
ADCQ	3	$1BDD	Direct	-	-	-	7
CMPQ	3	$1BDE	Direct	-	-	-	7
ADDQ	3	$1BDF	Direct	-	-	-	7

Opcodes $1BE0-$1BEF

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
ANDV	3	$1BE0	Indexed	-	-	-	8
ANDV	7	$1BE0	Indexed indirect	-	-	-	15
BITV	3	$1BE1	Indexed	-	-	-	8
BITV	7	$1BE1	Indexed indirect	-	-	-	15
EORV	3	$1BE2	Indexed	-	-	-	8
EORV	7	$1BE2	Indexed indirect	-	-	-	15
ORV	3	$1BE3	Indexed	-	-	-	8
ORV	7	$1BE3	Indexed indirect	-	-	-	15
MULOU	3	$1BE8	Indexed	-	-	-	76
MULOU	7	$1BE8	Indexed indirect	-	-	-	87
MULO	3	$1BE9	Indexed	-	-	-	78
MULO	7	$1BE9	Indexed indirect	-	-	-	89
ADCQ	3	$1BED	Indexed	-	-	-	8
ADCQ	7	$1BED	Indexed indirect	-	-	-	15
CMPQ	3	$1BEE	Indexed	-	-	-	8
CMPQ	7	$1BEE	Indexed indirect	-	-	-	15
ADDQ	3	$1BEF	Indexed	-	-	-	8
ADDQ	7	$1BEF	Indexed indirect	-	-	-	15

Opcodes $1BF0-$1BFF

Mnemonic	Bytes	Opcode	Addressing mode	MC6809	HD6309	63F09 16-bit	63F09 32-bit
ANDV	6	$1BF0	Extended	-	-	-	10
BITV	6	$1BF1	Extended	-	-	-	10
EORV	6	$1BF2	Extended	-	-	-	10
ORV	6	$1BF3	Extended	-	-	-	10
MULOU	6	$1BF8	Extended	-	-	-	78
MULO	6	$1BF9	Extended	-	-	-	80
ADCQ	6	$1BFD	Extended	-	-	-	10
CMPQ	6	$1BFE	Extended	-	-	-	10
ADDQ	6	$1BFF	Extended	-	-	-	10

Internal registers

63F09 — 2024-05-28T12:24:57Z

MD register is always accessible as it changes the processor's operating mode. Due to internal data path, 0 or Z (zero) register is available for transfer and exchange instructions.

6809 mode

Registers
8 bits	8 bits
A	B
Virtual D (16 bits)
Z
DP
CC
MD

16 bits
X
Y
U
S
PC

MD bits

MD
DZ	IL	FPU	32	IS	ED	FM	EM

EM:
- 0: 6809 mode
- 1: 6309 mode
FM:
- 0: FIRQ and EIRQ's treated as fast interrupt requests
- 1: FIRQ and EIRQ's treated as interrupt request
ED:
- 0: EIRQ [1] active on level
- 1: EIRQ active on falling edge
IS :
- 0: interrupt requests are not disabled after an interrupt routine is called.
- 1: interrupt requests are disabled after an interrupt routine is called until S stack pointer is loaded with a new value. Used to change CPU context with MMU.
32 : ignored if EM is set to 0.
- 0 : 6309 mode (16 bits)
- 1 : 63F09 mode (32 bits)
FPU : ignored if EM is set to 0.
- 0 : no FPU
- 1 : IEEE FPU
IL : output flag, illegal instruction
DZ : output flag, division by zero

6309 mode

Registers
8 bits	8 bits	8 bits	8 bits
A	B	E	F
Virtual D (16 bits)		Virtual W (16 bits)
Virtual Q (32 bits)
Z
DP
CC
MD

16 bits
X
Y
U
S
V
PC

63F09 mode

Note that 63F09 in full 63F09 mode does not contain 0 or Z (zero) register. 63F09 is a 32 bits extension of regular 6309.

Registers
8 bits	8 bits	8 bits	8 bits	8 bits
A	B	E	F	unaddressables
Virtual D (16 bits)		Virtual W (16 bits)		unaddressables
Virtual Q (32 bits)				V
Virtual O (64 bits)
MD (24 bits) EIRQ's mask			6309's MD
DS (16 bits)
DP
CC

32 bits
X
Y
U
S
PC

63F09 mode with FPU

Registers
8 bits	8 bits	8 bits	8 bits	8 bits
A	B	E	F	unaddressables
Virtual D (16 bits)		Virtual W (16 bits)		unaddressables
Virtual Q (32 bits)				V
Virtual O (64 bits)
MD (24 bits) EIRQ's mask			6309's MD
DS (16 bits)
DP
CC

32 bits
X
Y
U
S
PC

Please note that MD register is in 63F09 mode a 32 bits register. Eight LSB bits act as 6309 standard MD register. Other bits are used as EIRQ masks.

64 bits (single and double precision floating point registers)

FP0

FP1

FP2

FP3

FP4

FP5

FP6

FP7

FP8

FP9

FP10

FP11

FP12

FP13

FP14

FP15

8 bits
FPUCC

FPUCC
FPUCC contains three bits for rounding mode and five bits for status. It cannot be direcly addressed.

FPUCC
RND2	RND1	RND0	NV	DZ	OF	UF	NX

RND2, RND1, RND0 are set by SETRNE, SETRTZ, SETRDN, SETRUP, SETRMM or SETDYN instruction.
other bits are used as flags set by FPU:
- NV : invalid result
- DZ : division by zero
- OF : overflow
- UF : underflow
- NX : inexact

These flags can be tested by (L)BNV, (L)BDZ, (L)BOV, (L)BUN and (L)BIX instructions. FxCMPy returns result in CC, not in FPU flags register. Thus, other branch instructions (BEQ for example) can be used.

[1] EIRQ (extended interrupt request): 24 new hardware interrupt requests available in 63F09 mode.

FPU

63F09 — 2024-05-28T12:24:09Z

The floating-point unit 63F39

The 63F09's FPU is split cleanly in two: a 16-level register stack hosted in the CPU core itself, and a separate, stateless execution engine (referred to as 63F39) that the core drives through a small request/response interface. The core owns all FPU state; the engine only computes.

A 16-level, RPN-style operand stack, not a flat register file

REG_FP is sixteen 64-bit registers, REG_FP(0) to REG_FP(15) — but software addresses them as stack levels, not fixed register numbers: REG_FP(0) is always the top of the stack. Every FPU instruction ultimately drives one value into FP_STACK_CTRL (type FP_STACK_TYPE), decoded in a single process on the falling edge of the internal clock, and the whole array shifts as one unit:

Push — every register moves up one slot (REG_FP(i+1)<=REG_FP(i) for i from 14 downto 0) and the new value lands in REG_FP(0). Used to load an operand from memory (LOAD_FROM_MEM_DATA) or from the integer side of the core (LOAD_FROM_O, moving the 64-bit pseudo register O = Q:V across).
Pop — every register moves down one slot, the vacated top entries are cleared to zero (DROP_FP, and its N-level generalization DROPN_FP).
Stack juggling — DUP_FP/DUP2_FP/SWAP_FP/OVER_FP/ ROT_FP cover the fixed, one- or two-level Forth-style primitives; DUPN_FP/DROPN_FP/ROLL_FP/ROLLD_FP/PICK_FP/EXG_FP generalize duplication, dropping, rotation and exchange to an arbitrary level, and CLEAR_FP empties the whole stack.

Feeding the execution engine

An operation reads its operands directly off the top of this stack. LOAD_FPU_ARG1/LOAD_FPU_ARG2/LOAD_FPU_ARG3 copy the top one, two or three levels into the engine's own input latches, and START_FPU raises FPU_IN.FP_EXE_I.ENABLE to actually launch the computation. Once the engine reports back, LOAD_FROM_FPU takes the 64-bit RESULT and the 5-bit IEEE exception FLAGS, and LOAD_CCFPU updates just the flags without touching the stack at all — the path a comparison uses (see below).

Whether consuming a value counts as a real pop is a single bit, FP_STACK_CONF (FP_STACK_CONF_KEEP_ARGS vs FP_STACK_CONF_DISCARD_ARGS, itself selected by one bit of the opcode): with discard, LOAD_FPU_ARGn shifts the consumed levels away and LOAD_FROM_FPU pushes the result on top — a normal, stack-popping operation, net stack effect one level shallower per result produced. With keep, neither shift happens at all: LOAD_FPU_ARGn reads the operands in place and LOAD_FROM_FPU simply overwrites REG_FP(0) with the result — the stack depth is unchanged, and any operand below the top (REG_FP(1) and beyond) survives untouched for a following operation to reuse. This is what lets a value outlive the operation that reads it, without a manualDUP beforehand.

The execution engine itself

fp_exe_in_type/fp_exe_out_type (fp_wire.vhd) define the engine's own interface: three 64-bit operands, a one-hot fp_operation_type selector (fmadd/fmsub/fnmadd/fnmsub, fadd/fsub/fmul/fdiv/fsqrt, fsgnj, fcmp, fmax, fclass, fmv_i2f/fmv_f2i, fcvt_f2f/fcvt_i2f/fcvt_f2i plus a 2-bit fcvt_op sub-selector), a 2-bit format field and a 3-bit rounding-mode field — the same shape as a RISC-V “F/D” extension unit. The engine itself carries no stack, no state beyond one computation: the CPU-side stack machine described above is entirely what turns this generic, three-operand functional unit into the 63F09's own Forth-style FPU instruction set.

Private or shared: the FPU_BY_CORE choice

Everything above describes the interface between a core and an FPU engine — but on a multi-core build, that engine can be instantiated two different ways, selected by a single generic, FPU_BY_CORE, threaded down from the SoC top level through 63F81.vhd/63F29.vhd/ 63F09.vhd:

Per-core (FPU_BY_CORE=true) — each core gets its own private FP_UNIT instance, declared right inside the CPU core's own architecture (63F09.vhd, FPU_INTERFACE : if FPU_BY_CORE generate). No arbitration is needed at all: a core's REG_FP stack talks directly to an engine that belongs to it alone.
Shared (FPU_BY_CORE=false) — a single FP_UNIT instance lives at the top level instead (63F81.vhd, generate block SHARED_FPU), clocked by the chip-level E — the current bus master's own E, from the same arbiter described in the companion document. Every core still drives its own FPU_IN(i) entry (a per-core vector, fp_unit_in_vector_type) exactly as if it owned the engine outright, but only one entry at a time is actually multiplexed into the real unit's input (FPU_MUX_IN <= FPU_IN (CURRENT_CPU)), and the engine's single output, FPU_OUT, is wired back identically to every core's FPU_63F39_OUT port — the same signal, broadcast. A core only sees a meaningful result once the arbiter has actually picked its own request.

The arbiter that picks CURRENT_CPU mirrors the bus arbiter almost line for line: on each falling edge of E, a round robin starting from the currently-selected core (FPU_ACTIVE_CPU) looks for the first core whose FP_EXE_I.ENABLE is asserted, and sticks with whichever core it finds for as long as that core keeps its own ENABLE raised — the same “sticky, self-first” pattern as SIGNAL_LAST_ACTIVE_CPU for the bus, just applied to the FPU request instead of the bus request. A core that loses the race simply waits, its own ENABLE still high, until the current holder releases the engine and the round robin reaches it.

Comparisons: result goes to the CPU's own flags, not the stack

fcmp is the one operation that does not produce a floating-point value: it feeds LOAD_CCFPU instead of LOAD_FROM_FPU, so the comparison's outcome only ever updates REG_CCFPU's exception flags — the actual true/false predicate is delivered to the CPU's own condition codes (Z), the same register a plain integer CMPx would set. A comparing instruction therefore never touches the operand stack itself; a non-popping variant leaves both compared values exactly where they were.

Status and rounding mode: REG_CCFPU

REG_CCFPU is a single 8-bit register, split in two: bits 7-5 hold the current IEEE-754 rounding mode, set by six dedicated stack-control values (SET_RNE_FP/SET_RTZ_FP/SET_RDN_FP/SET_RUP_FP/ SET_RMM_FP/SET_DYN_FP — nearest-even, toward-zero, downward, upward, nearest-max-magnitude, or the dynamic mode driven by whatever the engine itself decides); bits 4-0 are the sticky IEEE exception flags (invalid, divide-by-zero, overflow, underflow, inexact) from the last operation that actually ran, refreshed by LOAD_FROM_FPU or LOAD_CCFPU.

Saving and restoring the stack

The full 16-level stack can be pushed to or pulled from memory one byte at a time — PULL_FP steers each incoming byte to the right slice of REG_FP(0) under a one-hot byte selector (REG_FP_BYTE), and PULL_DUP_FP additionally pushes a fresh level before landing the first byte, so a full 8-byte transfer naturally grows the stack by one level per value restored. A separate control, REG_FP_LIMIT, lets this transfer stop after fewer than sixteen levels — the mechanism behind the partial-stack save/restore instructions, which only move as many levels as a function actually uses instead of always paying for the full sixteen.

A 8/64 bits CPU

63F09 — 2024-05-28T12:08:18Z

63F09 is a modern CPU full compatible with old MC6809. It presents only one difference with HD6309, it don't have a 0 register.

If the first instruction after reset is LDMD, CPU can enter in 6309 mode (16 bits) or 63F09 mode (32 bits) with or without FPU.

In 63F09 mode, there are a lot of new instructions. For example:

hardwired multiplications and division (until 64 bits);
32 and 64 bits arithmetic;
FPU that handle simple and double precision floats;
32 bits addresses (36 bits with MMU)...

Twenty-seven interrupt requests are available:

NMI
IRQ
FIRQ
twenty-four EIRQ (extended interrupt requests) active on edge or level. These interrupt requests can be configured to act as a regular or fast interrupt.

63F09 clock is given by an external TTL clock running at 24 MHz. This clock cannot be modified without reconfiguration of internal PLL.